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1.发明申请Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US20100237923A1
公开(公告)日：2010-09-23
申请号：US12661156
申请日：2010-03-11
IPC分类号： H03H11/26 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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2.发明授权Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US08307320B2
公开(公告)日：2012-11-06
申请号：US12661156
申请日：2010-03-11
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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公开(公告)号：US07755530B2
公开(公告)日：2010-07-13
申请号：US12218531
申请日：2008-07-16
IPC分类号： H03M1/60
CPC分类号： H03M1/502
摘要： An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.
摘要翻译： A / D转换器具有一系列M个延迟单元，根据模拟信号的电平，在每个延迟单元中延迟延迟时间，脉冲信号通过该延迟单元被发送。 转换器的单位在N个采样时间中锁存从每个延迟单元输出的脉冲信号，以保持M×N个锁存数据。 转换器的另一单元接收M×N个锁存数据作为由按脉冲信号中的M×N个采样点的排列次序排列的锁存数据组成的一组合数据，将组合数据转换成 数字数据对应于延迟单元中的脉冲信号的位置，并且产生与来自数字数据的模拟信号的电平对应的转换的数字数据。
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公开(公告)号：US06940443B2
公开(公告)日：2005-09-06
申请号：US10942097
申请日：2004-09-16
CPC分类号： H03M1/06 , G04F10/005 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An A/D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A/D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.
摘要翻译： A / D转换器具有包括多个反相电路的脉冲延迟电路，其中通过第一对电源线输入模拟电压信号。 每个反相电路具有第一逻辑门。 所述A / D转换器具有逻辑电路，所述逻辑电路具有第二逻辑门和第二对电源线，所述逻辑电路基于电源电压工作。 设置电压信号的电平的第一范围和电源电压的第二范围中的至少一个，以防止隧道电流流过第一成对电源线之间和第二配对电源 当第一和第二逻辑门中的至少一个操作时线路。
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公开(公告)号：US20050057388A1
公开(公告)日：2005-03-17
申请号：US10942097
申请日：2004-09-16
CPC分类号： H03M1/06 , G04F10/005 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An A/D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A/D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.
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公开(公告)号：US20100087966A1
公开(公告)日：2010-04-08
申请号：US12587555
申请日：2009-10-08
IPC分类号： G05D3/12
CPC分类号： G05D3/12
摘要： The physical quantity measuring apparatus includes a first function of generating voltage used for position-controlling a movable body, a second function of detecting a position of the movable body during a position detecting period, a third function of calculating a control amount necessary to keep the movable body at a predetermined position on the basis of a detection result by the second function, and causing the first function to generate a control voltage corresponding to the calculated control amount to keep the movable body at the predetermined position during a position controlling period, and a fourth function of setting the position detecting period and the position controlling period in a time-sharing manner so that the position detecting period and the position controlling period do not overlap with each other.
摘要翻译： 物理量测量装置包括产生用于位置控制可移动体的电压的第一功能，在位置检测期间检测可移动体的位置的第二功能，计算保持所述可移动体所需的控制量的第三功能 基于第二功能的检测结果在预定位置处的移动体，并且使第一功能产生与计算出的控制量对应的控制电压，以在位置控制期间将移动体保持在预定位置，以及 以分时方式设置位置检测期间和位置控制期间的第四功能，使得位置检测期间和位置控制期间彼此不重叠。
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7.发明申请Method of transmitting modulated signals multiplexed by frequency division multiplexing and physical quantity detector using this method 有权使用该方法发送通过频分复用复用的调制信号和物理量检测器的方法公开(公告)号：US20100054281A1
公开(公告)日：2010-03-04
申请号：US12462043
申请日：2009-07-28
CPC分类号： G01C19/00 , G01C19/56 , G01P15/125 , G01P15/131 , G01P15/18 , H04L27/2601
摘要： A transmitting method has steps of modulating carrier waves having frequencies set at ½N−n (n≦N; n is a positive integer) of a reference frequency with transmission signals to produce modulated signals, multiplexing the modulated signals by frequency division multiplexing to produce an input signal, and transmitting the input signal to a synchronous detector in which the transmission signals are extracted from the input signal by calculating a moving average of the input signal every sampling period of time corresponding to the reference frequency and performing an addition and subtraction calculation corresponding to the cycle of each carrier wave for the moving averages. The frequency of each carrier wave, modulated with one transmission signal having a first signal level, is equal to or lower than the frequency of any carrier wave modulated with another transmission signal having a second signal level higher than the first signal level.
摘要翻译： 发送方法具有如下步骤：利用发送信号调制具有参考频率的1/2N-n（n＆nlE; N是正整数）的频率的载波，以产生调制信号，通过频分多路复用调制信号以产生 输入信号，并将输入信号发送到同步检测器，其中从输入信号中提取发送信号，通过计算与参考频率相对应的每个采样周期的输入信号的移动平均值，并对其进行相加和减法计算 到移动平均线的每个载波的周期。 用具有第一信号电平的一个发送信号调制的每个载波的频率等于或低于用具有高于第一信号电平的第二信号电平的另一传输信号调制的任何载波的频率。
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公开(公告)号：US07330144B2
公开(公告)日：2008-02-12
申请号：US11543259
申请日：2006-10-05
CPC分类号： H03M1/1019 , H03M1/0636 , H03M1/0678 , H03M1/1225 , H03M1/20 , H03M1/50 , H03M1/502 , H03M1/60
摘要： In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.
摘要翻译： 在模拟 - 数字转换器中，生成单元基于模数转换特性曲线执行第一输入信号和第二输入信号的模数转换，分别产生第一数字数据和第二数字数据 对应于第一输入信号和第二输入信号。 输入信号具有第一电平，第一电平是用于模数转换的目标模拟信号的偏移电平和电平之和。 第二输入信号具有第二电平，并且通过从目标模拟信号的电平减去偏移电平来产生第二电平。 在模数转换器中，获取单元获得第一数字数据和第二数字数据之间的差数字数据，以将获得的差分数字数据作为目标模拟信号的数字数据输出。
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9.发明授权Method of transmitting modulated signals multiplexed by frequency division multiplexing and physical quantity detector using this method 有权使用该方法发送通过频分复用复用的调制信号和物理量检测器的方法公开(公告)号：US08213437B2
公开(公告)日：2012-07-03
申请号：US12462043
申请日：2009-07-28
IPC分类号： H04L7/08
CPC分类号： G01C19/00 , G01C19/56 , G01P15/125 , G01P15/131 , G01P15/18 , H04L27/2601
摘要： A transmitting method has steps of modulating carrier waves having frequencies set at ½N−n (n≦N; n is a positive integer) of a reference frequency with transmission signals to produce modulated signals, multiplexing the modulated signals by frequency division multiplexing to produce an input signal, and transmitting the input signal to a synchronous detector in which the transmission signals are extracted from the input signal by calculating a moving average of the input signal every sampling period of time corresponding to the reference frequency and performing an addition and subtraction calculation corresponding to the cycle of each carrier wave for the moving averages. The frequency of each carrier wave, modulated with one transmission signal having a first signal level, is equal to or lower than the frequency of any carrier wave modulated with another transmission signal having a second signal level higher than the first signal level.
摘要翻译： 发送方法具有如下步骤：利用发送信号调制具有参考频率的1/2N-n（n＆nlE; N是正整数）的频率的载波，以产生调制信号，通过频分多路复用调制信号以产生 输入信号，并将输入信号发送到同步检测器，其中从输入信号中提取发送信号，通过计算与参考频率相对应的每个采样周期的输入信号的移动平均值，并对其进行相加和减法计算 到移动平均线的每个载波的周期。 用具有第一信号电平的一个发送信号调制的每个载波的频率等于或低于用具有高于第一信号电平的第二信号电平的另一传输信号调制的任何载波的频率。
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公开(公告)号：US20090021407A1
公开(公告)日：2009-01-22
申请号：US12218531
申请日：2008-07-16
CPC分类号： H03M1/502
摘要： An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.
摘要翻译： A / D转换器具有一系列M个延迟单元，根据模拟信号的电平，在每个延迟单元中延迟延迟时间，脉冲信号通过该延迟单元被发送。 转换器的单元在N个采样时间中锁存从每个延迟单元输出的脉冲信号，以保持MxN锁存数据。 转换器的另一单元接收M×N个锁存数据作为由按脉冲信号中的M×N个采样点的排列顺序排列的锁存数据组成的一组合数据，将组合数据转换为数字数据 一次延迟到延迟单元中的脉冲信号的位置，并产生对应于来自数字数据的模拟信号电平的转换的数字数据。
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