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1.发明授权Semiconductor device with NMOS including Si:C channel region and/or PMOS including SiGe channel region 失效具有NMOS的半导体器件包括Si：C沟道区和/或包括SiGe沟道区的PMOS公开(公告)号：US06774409B2
公开(公告)日：2004-08-10
申请号：US10092729
申请日：2002-03-08
申请人： Tomoya Baba , Katsumasa Fujii , Akiyoshi Mutou
发明人： Tomoya Baba , Katsumasa Fujii , Akiyoshi Mutou
IPC分类号： H01L218234
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/1054
摘要： A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.
摘要翻译： 半导体器件包括：半导体衬底，其上依次形成硅锗膜，含碳硅膜和硅膜，并且在半导体衬底上形成栅电极，其中介入了栅氧化膜，其中沟道区 的半导体器件形成在含碳硅膜中，或者其中半导体器件的沟道区形成在硅锗膜中。
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公开(公告)号：US6140189A
公开(公告)日：2000-10-31
申请号：US248630
申请日：1999-02-11
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0266 , Y10S438/981
摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.
摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。
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公开(公告)号：US06524893B2
公开(公告)日：2003-02-25
申请号：US10002108
申请日：2001-12-05
申请人： Hidechika Kawazoe , Eiji Aoki , Sheng Teng Hsu , Katsumasa Fujii
发明人： Hidechika Kawazoe , Eiji Aoki , Sheng Teng Hsu , Katsumasa Fujii
IPC分类号： H01L21332
CPC分类号： H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L29/7412
摘要： An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.
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公开(公告)号：US4686974A
公开(公告)日：1987-08-18
申请号：US904021
申请日：1986-09-02
CPC分类号： A61M16/00 , A61M16/0677 , A61M2016/0021
摘要： Steady insufflation of a gas starts before the beginning of each inhalation, and a pulse-like peak flow insufflation of the gas is superposed on the steady insufflation for a short period of times at the beginning of the inhalation, and the steady insufflation is terminated before the end of the inhalation, so as to improve the inhalation efficiency of insufflated gas extremely.
摘要翻译： 在每次吸入开始之前，气体的稳定吹气开始，并且在吸入开始时，气体的脉冲状峰值流量吹入在持续吹入时间较短的时间段内叠加，并且稳定吹气在 吸入结束，极大地提高吸入气体的吸入效率。
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5.发明授权公开(公告)号：US08129768B2
公开(公告)日：2012-03-06
申请号：US11802706
申请日：2007-05-24
IPC分类号： H01L29/772
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/823807 , H01L27/092 , H01L27/15 , H01L29/0673 , H01L29/78654 , H01L29/78681 , H01L29/78684 , H01L29/78696 , Y10S977/762 , Y10S977/781 , Y10S977/789
摘要： An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.
摘要翻译： 本发明的集成电路器件包括其上提供至少两种类型的纳米线元件的衬底。 这些纳米线元件具有彼此不同的功能和材料。 纳米线元件由具有与纳米线元件的类型不同的尺寸的纳米线构成。 与包括其上提供有一种类型的纳米线元件的基板的集成电路器件相比，可以显着地提高集成电路器件的功能。
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公开(公告)号：US20110284380A1
公开(公告)日：2011-11-24
申请号：US13113680
申请日：2011-05-23
申请人： Samuel MARTIN , Xiangfeng Duan , Katsumasa Fujii , James M. Hamilton , Hiroshi Iwata , Francisco Leon , Jeffrey Miller , Tetsu Negishi , Hiroshi Ohki , J. Wallace Parce , Cheri X.Y. Pereira , Paul John Schuele , Akihide Shibata , David P. Stumbo , Yasunobu Okada
发明人： Samuel MARTIN , Xiangfeng Duan , Katsumasa Fujii , James M. Hamilton , Hiroshi Iwata , Francisco Leon , Jeffrey Miller , Tetsu Negishi , Hiroshi Ohki , J. Wallace Parce , Cheri X.Y. Pereira , Paul John Schuele , Akihide Shibata , David P. Stumbo , Yasunobu Okada
CPC分类号： H01L29/0665 , B82B3/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L29/0673 , Y10S977/883
摘要： The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
摘要翻译： 本发明提供了用于纳米线对准和沉积的方法和系统。 使用通电（例如，交流电场）来使纳米线与电极对准和关联。 通过调节激励，纳米线耦合到电极，使得它们在随后的洗涤和干燥步骤期间保持在适当的位置。 本发明还提供了将纳米线从一个衬底转移到另一个衬底以便制备各种器件衬底的方法。 本发明还提供了用于监测和控制在特定电极对上沉积的纳米线的数量的方法，以及用于操纵溶液中的纳米线的方法。
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公开(公告)号：US20060006412A1
公开(公告)日：2006-01-12
申请号：US11219671
申请日：2005-09-07
申请人： Masahiro Takenaka , Katsumasa Fujii
发明人： Masahiro Takenaka , Katsumasa Fujii
IPC分类号： H01L31/0328
CPC分类号： H01L29/165 , H01L21/76254 , H01L29/1054
摘要： A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or in combination on the above semiconductor substrate and a method of manufacturing the above semiconductor substrate.
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公开(公告)号：US5910673A
公开(公告)日：1999-06-08
申请号：US984801
申请日：1997-12-04
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L23/62
CPC分类号： H01L27/0266 , Y10S438/981
摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.
摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。
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公开(公告)号：US4947232A
公开(公告)日：1990-08-07
申请号：US277440
申请日：1988-11-28
CPC分类号： H01L29/405 , H01L29/7835
摘要： A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.
摘要翻译： 金属氧化物半导体器件的特征在于，设置用于覆盖半导体器件的沟道区域的覆盖元件，其间插入有绝缘层。 覆盖元件连接到从漏电极，源电极和栅电极中选择的至少一个电极。 因此，覆盖元件的电平是固定的。
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10.发明授权公开(公告)号：US06696730B2
公开(公告)日：2004-02-24
申请号：US10003321
申请日：2001-12-06
申请人： Hidechika Kawazoe , Eiji Aoki , Sheng Teng Hsu , Katsumasa Fujii
发明人： Hidechika Kawazoe , Eiji Aoki , Sheng Teng Hsu , Katsumasa Fujii
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L29/7412
摘要： An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.
摘要翻译： 在半导体集成电路的输入或输出端设有静电放电保护装置，用于保护内部电路免受流入或流出集成电路的静电浪涌。 静电放电保护装置可以包括晶闸管和用于触发晶闸管的触发二极管（例如，以低电压）。 触发二极管可以包括n型阴极高杂质浓度区域; p型阳极杂质浓度高的区域; 以及用于将形成在阴极区域的表面上的硅化物层与形成在阳极区域的表面上的另一硅化物层电绝缘的绝缘体部分。
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