公开(公告)号：US06696730B2

公开(公告)日：2004-02-24

申请号：US10003321

申请日：2001-12-06

申请人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

发明人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L29/7412

摘要： An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.

摘要翻译： 在半导体集成电路的输入或输出端设有静电放电保护装置，用于保护内部电路免受流入或流出集成电路的静电浪涌。 静电放电保护装置可以包括晶闸管和用于触发晶闸管的触发二极管（例如，以低电压）。 触发二极管可以包括n型阴极高杂质浓度区域; p型阳极杂质浓度高的区域; 以及用于将形成在阴极区域的表面上的硅化物层与形成在阳极区域的表面上的另一硅化物层电绝缘的绝缘体部分。

公开(公告)号：US06338986B1

公开(公告)日：2002-01-15

申请号：US09379108

申请日：1999-08-23

申请人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

发明人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L29/7412

摘要： An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

摘要翻译： 根据本发明的静电放电保护装置设置在用于保护半导体集成电路的内部电路免受流入或流出半导体集成电路的静电浪涌的半导体集成电路的输入或输出。 静电放电保护装置包括：晶闸管; 以及用于以低电压触发晶闸管的触发二极管。 触发二极管包括：n型阴极高杂质浓度区域; p型阳极杂质浓度高的区域; 以及用于将形成在n型阴极高杂质浓度区域的表面上的硅化物层与形成在p型阳极高杂质浓度区域的表面上的另一硅化物层电绝缘的绝缘体部分。

公开(公告)号：US06524893B2

公开(公告)日：2003-02-25

申请号：US10002108

申请日：2001-12-05

申请人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

发明人： Hidechika Kawazoe ,  Eiji Aoki ,  Sheng Teng Hsu ,  Katsumasa Fujii

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L29/7412

摘要： An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

公开(公告)号：US6140189A

公开(公告)日：2000-10-31

申请号：US248630

申请日：1999-02-11

申请人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0266 ,  Y10S438/981

摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

公开(公告)号：US5910673A

公开(公告)日：1999-06-08

申请号：US984801

申请日：1997-12-04

申请人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L23/62

CPC分类号： H01L27/0266 ,  Y10S438/981

摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

公开(公告)号：US07905013B2

公开(公告)日：2011-03-15

申请号：US11809959

申请日：2007-06-04

申请人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

IPC分类号： H01K3/10

CPC分类号： A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

摘要翻译： 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

公开(公告)号：US07811913B2

公开(公告)日：2010-10-12

申请号：US11312967

申请日：2005-12-19

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/265

CPC分类号： H01L31/105 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S438/933

摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

摘要翻译： 制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

公开(公告)号：US07759756B2

公开(公告)日：2010-07-20

申请号：US12025618

申请日：2008-02-04

申请人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

IPC分类号： H01L31/00 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14647 ,  H01L27/14689

摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.

摘要翻译： 提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。 两个独立像素用于三色检测。 第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。 两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。 底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。 顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。 单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

公开(公告)号：US07723729B2

公开(公告)日：2010-05-25

申请号：US12036396

申请日：2008-02-25

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L31/0312 ,  H01L29/20 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/045 ,  H01L29/0673

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

公开(公告)号：US07651883B2

公开(公告)日：2010-01-26

申请号：US11801320

申请日：2007-05-09

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14689

摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.

摘要翻译： 提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。 彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。 在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。 光电二极管组包括形成为堆叠多结结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。 阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。