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    SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING FINE STRUCTURE ARRANGING SUBSTRATE, AND DISPLAY ELEMENT
    3.
    发明申请
    SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING FINE STRUCTURE ARRANGING SUBSTRATE, AND DISPLAY ELEMENT 审中-公开
    半导体元件，制造微结构基板的方法和显示元件

    公开(公告)号：US20110058126A1

    公开(公告)日：2011-03-10

    申请号：US12867725

    申请日：2009-02-10

    申请人： Yasunobu Okada ,  Akihide Shibata ,  Yoshiharu Nakajima ,  Hiroshi Iwata ,  Ai Naitou ,  Yutaka Takafuji ,  Tetsu Negishi

    发明人： Yasunobu Okada ,  Akihide Shibata ,  Yoshiharu Nakajima ,  Hiroshi Iwata ,  Ai Naitou ,  Yutaka Takafuji ,  Tetsu Negishi

    IPC分类号： G02F1/1333 ,  H01L29/41 ,  H01L21/44

    CPC分类号： H01L27/283 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/78696 ,  H01L51/0012 ,  H01L51/0545

    摘要： With reference to a direction perpendicular to a direction of forming electrodes to which a voltage can be applied, fine structures are each arranged within ±5 degrees at a substantially even interval, and a semiconductor element is formed by using the fine structures. On an insulating substrate, at least two electrodes are arranged at a predetermined interval, and there are formed one or more fine structure arranging regions, each of which is formed by a unit of the two electrodes. A semiconductor element electrode is made in contact with the plurality of the fine structures, each having two ends in contact with the two electrodes and a length in a longitudinal direction of a nano order to a micron order, and arranged within ±5 degrees with reference to the direction perpendicular to the direction of forming the electrodes.

    摘要翻译： 关于与形成可施加电压的电极的方向垂直的方向，精细结构以基本上均匀的间隔布置在±5度内，并且通过使用精细结构形成半导体元件。 在绝缘基板上，至少两个电极以预定间隔布置，并且形成一个或多个精细结构布置区域，每个电极由两个电极的单元形成。 半导体元件电极与多个精细结构接触，每个微结构具有与两个电极接触的两个端部，并且在纵向方向上的长度为纳米级至微米级，并且以参考方式布置在±5度内 到垂直于形成电极的方向的方向。

    Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device
    10.
    发明授权
    Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device 有权
    半导体存储器件，页缓冲器资源分配方法及其电路，计算机系统和移动电子设备

    公开(公告)号：US07405974B2

    公开(公告)日：2008-07-29

    申请号：US10848324

    申请日：2004-05-19

    申请人： Yoshifumi Yaoi ,  Yasuaki Iwase ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

    发明人： Yoshifumi Yaoi ,  Yasuaki Iwase ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

    IPC分类号： G11C16/00

    CPC分类号： G11C16/10 ,  G11C7/10 ,  G11C7/1039 ,  G11C2207/2245

    摘要： A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

    摘要翻译： 半导体存储器件包括页缓冲电路和存储元件的布置，每个存储元件包括：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有存储电荷功能的记忆功能部件。 页面缓冲电路提供了在存储器阵列控制器和用户之间共享的公共资源。 页面缓冲电路具有包含随机存取存储器阵列的两个平面。 页面缓冲电路还包括模式控制部分，以便以用户模式访问主总线上的平面并且以存储器控制模式通过存储器阵列控制器访问平面。