公开(公告)号：US08785301B2

公开(公告)日：2014-07-22

申请号：US13390869

申请日：2011-02-25

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

IPC分类号： H01L21/322 ,  H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/02057 ,  H01L21/67051 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

摘要： A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.

摘要翻译： 清洗SiC半导体的方法包括以下步骤：在SiC半导体的表面形成氧化膜，除去氧化物膜。 在形成氧化膜的步骤中，使用浓度大于或等于30ppm的臭氧水形成氧化膜。 成形步骤优选包括加热SiC半导体的表面和臭氧水中的至少一个的步骤。 因此，可以获得能够对SiC半导体具有清洁效果的SiC半导体的清洗方法。

公开(公告)号：US08564017B2

公开(公告)日：2013-10-22

申请号：US13485423

申请日：2012-05-31

申请人： Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

发明人： Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/66 ,  H01L21/337 ,  H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068

摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j

摘要翻译： 漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。 身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

公开(公告)号：US08513676B2

公开(公告)日：2013-08-20

申请号：US13512459

申请日：2010-12-17

申请人： Shin Harada ,  Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

发明人： Shin Harada ,  Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

IPC分类号： H01L29/38

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/049 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/94

摘要： A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −3° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm−3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.

摘要翻译： 一种半导体器件包括：由碳化硅制成的衬底，其具有相对于（0-33-8）面的偏离角不小于-3°且不大于+ 5°的主表面， 10方向; 由碳化硅制成的p型层，通过外延生长形成在衬底的主表面上; 以及形成为与p型层的表面接触的氧化物膜。 在p型层和氧化膜之间的界面10nm以内的区域中，氮原子浓度的最大值为1×1021cm-3以上。

公开(公告)号：US20120313112A1

公开(公告)日：2012-12-13

申请号：US13490208

申请日：2012-06-06

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813

摘要： A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm−3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.

摘要翻译： MOSFET包括碳化硅衬底，由碳化硅制成的漂移层，并且包括相对于{0001}面具有50°以上且65°以下的偏离角的主表面，以及形成在 并与漂移层的主表面接触。 漂移层包括形成为包括与栅氧化膜接触的区域的p型体区。 p型体区的杂质浓度为5×10 16 cm -3以上。 在垂直于漂移层的厚度方向的方向上彼此分离的p导电类型的多个p型区域布置在位于p型体区域和碳化硅衬底之间的漂移层中的区域中。

公开(公告)号：US20120280255A1

公开(公告)日：2012-11-08

申请号：US13522216

申请日：2011-10-25

申请人： Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

发明人： Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/16 ,  H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

摘要： An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

摘要翻译： MOSFET包括碳化硅衬底，有源层，栅氧化物膜和栅电极。 有源层包括通过向栅电极施加电压而在与栅极氧化膜接触的区域处形成反型层的主体区域。 身体区域包括布置在反型层形成区域的低浓度区域，并且在反转层中包含低浓度杂质和与反转层中的载流子移动方向上的低浓度区域相邻的高浓度区域 形成反型层的区域，并且含有浓度高于低浓度区域的杂质。

公开(公告)号：US09000447B2

公开(公告)日：2015-04-07

申请号：US13613838

申请日：2012-09-13

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

IPC分类号： H01L29/15 ,  H01L21/04 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

摘要翻译： 第一层具有n型导电性。 第二层外延形成在第一层上并具有p型导电性。 第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。 其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。 提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。 栅极绝缘膜覆盖栅极沟槽的侧壁。 栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

公开(公告)号：US20130078771A1

公开(公告)日：2013-03-28

申请号：US13613858

申请日：2012-09-13

申请人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

发明人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC分类号： H01L21/331

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/7395

摘要： A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.

摘要翻译： 具有p型的集电极层形成在具有n型的碳化硅衬底上。 在集电体层的顶面侧形成有n型漂移层。 设置在漂移层上并具有p型的体区，并且形成设置在身体区域上以通过身体区域与移动层分离并具有n型的发射极区域。 通过去除碳化硅衬底来暴露集电极层的底表面侧。

公开(公告)号：US20130075759A1

公开(公告)日：2013-03-28

申请号：US13613838

申请日：2012-09-13

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

IPC分类号： H01L29/161

CPC分类号： H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

摘要翻译： 第一层具有n型导电性。 第二层外延形成在第一层上并具有p型导电性。 第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。 其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。 提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。 栅极绝缘膜覆盖栅极沟槽的侧壁。 栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

公开(公告)号：US20130065384A1

公开(公告)日：2013-03-14

申请号：US13613785

申请日：2012-09-13

申请人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

发明人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/0475 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7397

摘要： A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

摘要翻译： 通过沉积方法在碳化硅层上形成掩模层。 掩模层被图案化。 通过使用图案化掩模层作为掩模的蚀刻去除碳化硅层的一部分来形成具有侧壁的栅极沟槽。 栅极绝缘膜形成在栅极沟槽的侧壁上。 在栅极绝缘膜上形成栅电极。 碳化硅层具有六方晶体和立方晶体中的一种，栅极沟槽的侧壁基本上包括{0-33-8}面和{01-1-4}面之一，在硅 碳化物层为六方晶系，并且在碳化硅层为立方晶型的情况下，基本上包含{100}面。

公开(公告)号：US20120326166A1

公开(公告)日：2012-12-27

申请号：US13529602

申请日：2012-06-21

申请人： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

发明人： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/24 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

摘要翻译： 衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。 基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。 栅极绝缘膜设置在基板的表面上。 在栅极绝缘膜上设置栅电极。