公开(公告)号：US5933436A

公开(公告)日：1999-08-03

申请号：US611818

申请日：1996-03-06

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

IPC分类号： G06F12/16 ,  G06F11/10 ,  H03M13/15 ,  G11C29/00

CPC分类号： G06F11/1008 ,  H03M13/151

摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

摘要翻译： 一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据 。

公开(公告)号：US6014330A

公开(公告)日：2000-01-11

申请号：US167969

申请日：1998-10-08

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5774397A

公开(公告)日：1998-06-30

申请号：US711652

申请日：1996-09-10

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5555204A

公开(公告)日：1996-09-10

申请号：US266633

申请日：1994-06-28

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C16/02

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5946231A

公开(公告)日：1999-08-31

申请号：US72664

申请日：1998-05-05

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

公开(公告)号：US06188611B1

公开(公告)日：2001-02-13

申请号：US09408441

申请日：1999-09-29

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US06545909B2

公开(公告)日：2003-04-08

申请号：US10094215

申请日：2002-03-11

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.

摘要翻译： 存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。 位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。 位线连接位线控制器和存储单元。 在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。 多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

公开(公告)号：US6044013A

公开(公告)日：2000-03-28

申请号：US314446

申请日：1999-05-19

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

摘要翻译： 提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。 位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。 当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。 具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。 结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

公开(公告)号：US06363010B1

公开(公告)日：2002-03-26

申请号：US09899290

申请日：2001-07-06

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

公开(公告)号：US5969985A

公开(公告)日：1999-10-19

申请号：US816830

申请日：1997-03-18

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.