公开(公告)号：US5933436A

公开(公告)日：1999-08-03

申请号：US611818

申请日：1996-03-06

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

IPC分类号： G06F12/16 ,  G06F11/10 ,  H03M13/15 ,  G11C29/00

CPC分类号： G06F11/1008 ,  H03M13/151

摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

摘要翻译： 一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据 。

公开(公告)号：US5602789A

公开(公告)日：1997-02-11

申请号：US518024

申请日：1995-08-22

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

摘要翻译： 用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路 以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路 在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

公开(公告)号：US5386422A

公开(公告)日：1995-01-31

申请号：US229761

申请日：1994-04-19

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

公开(公告)号：US6014330A

公开(公告)日：2000-01-11

申请号：US167969

申请日：1998-10-08

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5774397A

公开(公告)日：1998-06-30

申请号：US711652

申请日：1996-09-10

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5555204A

公开(公告)日：1996-09-10

申请号：US266633

申请日：1994-06-28

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C16/02

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5946231A

公开(公告)日：1999-08-31

申请号：US72664

申请日：1998-05-05

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

公开(公告)号：US5469444A

公开(公告)日：1995-11-21

申请号：US341955

申请日：1994-11-16

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

公开(公告)号：US5321699A

公开(公告)日：1994-06-14

申请号：US851286

申请日：1992-03-12

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

公开(公告)号：US06188611B1

公开(公告)日：2001-02-13

申请号：US09408441

申请日：1999-09-29

申请人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

发明人： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。