公开(公告)号：US5574391A

公开(公告)日：1996-11-12

申请号：US453120

申请日：1995-05-30

申请人： Toshiaki Hanibuchi ,  Yasushi Hayakawa ,  Masahiro Ueda

发明人： Toshiaki Hanibuchi ,  Yasushi Hayakawa ,  Masahiro Ueda

IPC分类号： H03K19/086 ,  H03K19/013

CPC分类号： H03K19/0136

摘要： In an ECL circuit, when a potential of an input signal A changes from "L" to "H", an output signal D correspondingly changes from "H" to "L", and, at this time, an output sent from a switching stage circuit is supplied to a gate of a PMOS transistor via a control capacitor. Thereby, a base current of a pull-down transistor flows, and change of a potential of an output terminal node is promoted. An NMOS transistor receiving the potential of the output terminal node is arranged between a node and a VEE supply terminal. Therefore, when the potential changes, the current flowing through a transistor decreases, and the base current of the pull-down transistor further increases, so that the change of the output signal D is further promoted.

摘要翻译： 在ECL电路中，当输入信号A的电位从“L”变为“H”时，输出信号D相应地从“H”变为“L”，此时，从切换 经由控制电容器向PMOS晶体管的栅极提供级电路。 由此，下拉晶体管的基极电流流动，促进输出端子节点的电位变化。 接收输出端子节点的电位的NMOS晶体管配置在节点与VEE供电端子之间。 因此，当电位变化时，流过晶体管的电流减小，并且下拉晶体管的基极电流进一步增加，从而进一步促进输出信号D的变化。

公开(公告)号：US5561382A

公开(公告)日：1996-10-01

申请号：US392321

申请日：1995-02-22

申请人： Masahiro Ueda ,  Toshiaki Hanibuchi

发明人： Masahiro Ueda ,  Toshiaki Hanibuchi

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/082

CPC分类号： H03K19/017527 ,  H03K19/0008

摘要： The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an "L" to "H" transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic "H" at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.

摘要翻译： 当输入信号（CI）进行“L”到“H”转换时，中间信号（Y1）的逻辑变为高电平，然后晶体管（Q1）导通，晶体管（Q2）截止。 在CMOS电平对应于逻辑“H”的电位处的输入信号（CI）被施加到NMOS截止器（N1）的栅极，并且NMOS晶体管（N1）快速导通。 此时，仅流过输出晶体管（Q0）的基极的电流流过电阻器（R2）和NMOS晶体管（N1）的导通电阻的并联连接。 由于NMOS晶体管（N1）导通，如果电阻器（R2）具有高电阻，则输出晶体管（Q0）的基极电位升高，并且从输出晶体管（Q0）馈送的电流增加，从而提高发射极电位 的输出晶体管（Q0）。 然后输出信号（EO）的逻辑变高。 输出缓冲电路的功耗降低。

公开(公告)号：US5164617A

公开(公告)日：1992-11-17

申请号：US703870

申请日：1991-05-23

申请人： Toshiaki Hanibuchi ,  Masahiro Ueda

发明人： Toshiaki Hanibuchi ,  Masahiro Ueda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/04 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H01L27/0623 ,  H03K19/0136 ,  H03K19/09448

摘要： A signal applied through a signal input terminal is logically processed by a logic circuit such as a CMOS inverter and the processed signal is supplied from the signal output terminal. A pinch resistor has a resistance value controlled in accordance with a variation of a voltage at the signal output terminal. Specifically, the pinch resistor has a higher resistance value at an initial stage in the switching operation in which an output from the logic circuit lowers from a logical high level to a logical low level, and supplies a large base current to a bipolar transistor. At a later stage in the switching operation, the pinch resistor has a small resistance value, so that a residual charge in the signal output terminal and a base charge in the bipolar transistor are rapidly emitted through the pinch resistor. Thus, the resistance value of the pinch resistor is always maintained at an optimum value, which increases a speed of the switching operation of the logic circuit.

摘要翻译： 通过信号输入端施加的信号由CMOS反相器等逻辑电路进行逻辑处理，从信号输出端提供处理后的信号。 夹持电阻器具有根据信号输出端子处的电压变化而控制的电阻值。 具体地说，在逻辑电路的输出从逻辑高电平降低到逻辑低电平的开关动作中，钳位电阻在初始阶段具有较高的电阻值，并向双极型晶体管提供较大的基极电流。 在开关操作的稍后阶段，夹持电阻器具有小的电阻值，使得信号输出端子中的剩余电荷和双极晶体管中的基极电荷通过夹持电阻器快速发射。 因此，夹持电阻器的电阻值始终保持在最佳值，这增加了逻辑电路的开关操作速度。

公开(公告)号：US5317206A

公开(公告)日：1994-05-31

申请号：US980877

申请日：1992-11-24

申请人： Toshiaki Hanibuchi ,  Masahiro Ueda

发明人： Toshiaki Hanibuchi ,  Masahiro Ueda

IPC分类号： H03K17/16 ,  H03K5/01 ,  H03K17/567 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/07 ,  H03K5/12

CPC分类号： H03K19/00361 ,  H03K5/01

摘要： First and second capacitor circuits responsive to a potential applied to an input node for instantaneously supplying a voltage derived by capacitance division to control electrodes of first and second output MOS transistors which drive an output node. When the output node reaches a predetermined potential level, the control electrode node of the first output transistor or the control electrode node of the second output transistor is driven to ground potential or power supply potential by the MOS transistor responding to a delay signal of an input signal. A smaller buffer circuit which has improved output response and reduced through current is described. The output signal transitioning speed can also be easily altered.

摘要翻译： 响应于施加到输入节点的电位的第一和第二电容器电路，用于将由电容分压导出的电压瞬时提供给驱动输出节点的第一和第二输出MOS晶体管的控制电极。 当输出节点达到预定电位电平时，第一输出晶体管的控制电极节点或第二输出晶体管的控制电极节点由MOS晶体管响应输入的延迟信号被驱动到地电位或电源电位 信号。 描述了具有改善的输出响应和减小的通过电流的较小的缓冲电路。 输出信号转换速度也可以轻易改变。

公开(公告)号：US5072285A

公开(公告)日：1991-12-10

申请号：US482954

申请日：1990-02-22

申请人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Kimio Ueda

发明人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Kimio Ueda

IPC分类号： H01L21/8249 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H03K19/08

CPC分类号： H01L27/11896

摘要： A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming bipolar transistors comprises p-type source or drain region of the region for forming p-MOS transistors as a base region, and an n-type emitter region formed in the base region and a region for taking out the potential of substrate of the p-MOS transistor as a collector region. An npn bipolar transistor formed in the region for forming p-MOS transistors can be electrically isolated from the other p-MOS transistor and used by holding gates disposed at the opposite sides of the base region at a power supply potential.

摘要翻译： 双CMOS门阵列包括组合CMOS晶体管和双极晶体管的基本单元。 基本单元由用于形成p-MOS晶体管的区域，用于形成n-MOS晶体管的区域和用于形成双极晶体管的区域形成。 用于形成p-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的p型源极和漏极区域，以便设置在每个栅极的相对侧 并具有预定的宽度。 用于形成n-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的n型源极和漏极区域，以便设置在每个栅极的相对侧 并具有预定的宽度。 用于形成双极晶体管的区域包括用于形成p-MOS晶体管作为基极区域的区域的p型源极或漏极区域，以及形成在基极区域中的n型发射极区域和用于取出衬底的电位的区域 作为集电极区域的p-MOS晶体管。 在用于形成p-MOS晶体管的区域中形成的npn双极晶体管可以与另一个p-MOS晶体管电隔离，并且通过将栅极设置在基极区域的相对侧处于供电电位来使用。

公开(公告)号：US4992845A

公开(公告)日：1991-02-12

申请号：US294020

申请日：1989-01-06

申请人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

发明人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

IPC分类号： H01L21/82 ,  H01L27/118

CPC分类号： H01L27/11898

摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

摘要翻译： 在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2） 在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。 每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。 在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据 减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

公开(公告)号：US5173625A

公开(公告)日：1992-12-22

申请号：US744578

申请日：1991-08-14

申请人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Katsushi Asahina

发明人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Katsushi Asahina

IPC分类号： H01L27/04 ,  G05F3/22 ,  H01L21/822 ,  H03K19/0175 ,  H03K19/018

CPC分类号： H03K19/017518 ,  G05F3/22 ,  H03K19/017509

摘要： A level conversion apparatus for converting a signal of an ECL level into a signal of a TTL level is disclosed which has source voltages set to a potential corresponding to a lower limit logic swing of the ECL level and a potential corresponding to an upper limit logic swing of the TTL level. This level conversion apparatus includes a reference voltage generating circuit for generating an upper limit reference voltage and a lower limit reference voltage divided from a voltage applied between a source terminal Vcc and a ground terminal, a control signal generating circuit for generating a control signal in response to the ECL level signal, determined by a difference between the upper limit reference voltage and the lower limit reference voltage, and an output switching circuit for carrying out a switching operation in response to the controlled signal. The output switching circuit outputs a signal determined by the potential corresponding to the upper limit logic swing of the TTL level and a ground source.

摘要翻译： 公开了一种用于将ECL电平的信号转换成TTL电平的信号的电平转换装置，其将源极电压设置为对应于ECL电平的下限逻辑摆幅的电位和对应于上限逻辑摆幅的电位 的TTL电平。 该电平转换装置包括用于产生上限参考电压和从源极端子Vcc和接地端子之间施加的电压分开的下限参考电压的参考电压产生电路，用于响应地产生控制信号的控制信号发生电路 到由上限参考电压和下限参考电压之间的差确定的ECL电平信号和用于响应于受控信号执行开关操作的输出开关电路。 输出开关电路输出由与TTL电平的上限逻辑摆幅相对应的电位和地源确定的信号。

公开(公告)号：US4916385A

公开(公告)日：1990-04-10

申请号：US262302

申请日：1988-10-25

申请人： Ichiro Tomioka ,  Masahiro Ueda ,  Takahiko Arakawa ,  Toshiaki Hanibuchi ,  Yoshihiro Okuno

发明人： Ichiro Tomioka ,  Masahiro Ueda ,  Takahiko Arakawa ,  Toshiaki Hanibuchi ,  Yoshihiro Okuno

IPC分类号： G01R19/165 ,  G01R31/316 ,  G01R31/317 ,  G01R31/319 ,  H03K17/00 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0948

CPC分类号： H03K19/00361 ,  G01R31/316 ,  G01R31/31905

摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

摘要翻译： 公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。 逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。 在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。 响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。 缓慢上升的输出信号没有下冲或振铃。

公开(公告)号：US5148514A

公开(公告)日：1992-09-15

申请号：US515476

申请日：1990-04-24

申请人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

发明人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

IPC分类号： G06N3/063

CPC分类号： G06N3/063

摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.

摘要翻译： 具有Boltzmann模型学习功能的延伸定向集成电路装置包括多个突触，其表示以矩阵排列的单元，以形成包括半导体芯片上的第一和第二三角形的矩形，多个神经元表示单元和多个 沿矩形的第一和第二侧布置的教育者信号控制电路以及沿矩形的第三和第四侧布置的多个缓冲电路。 第一面与第三面相反，第二面与第四面相反。 轴突信号传输线和枝晶信号线被布置成使得表示单元的神经元在第二直角三角形的第一直角三角形的每一个中是全连接的。 或者，轴突信号线和枝晶信号与突触表示单位矩阵的行和列平行布置，使得表示单元的神经元表示在矩形中。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。

公开(公告)号：US07515639B2

公开(公告)日：2009-04-07

申请号：US12024885

申请日：2008-02-01

申请人： Toshiaki Hanibuchi

发明人： Toshiaki Hanibuchi

IPC分类号： H04B3/00

CPC分类号： H04L25/14 ,  H04L7/0008

摘要： An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal through the data signal transmission lines, depending on a transmit clock; and control transmitting units that transmit control signals through the control transmission lines, depending on the transmit clock. The receiver includes a receive clock generator that generates a read clock from the control signals; and a data receiving unit that receives the data signal through the data signal transmission line, depending on the read clock.

摘要翻译： 异步数据发送装置包括数据信号传输线; 分别具有最小延迟和最大延迟的两个控制传输线; 发射机 和接收器。 发射机包括数据发送单元，其根据发送时钟通过数据信号传输线路发送数据信号; 以及根据发送时钟通过控制传输线路发送控制信号的控制发送单元。 接收机包括从控制信号产生读时钟的接收时钟发生器; 以及数据接收单元，其根据读取的时钟通过数据信号传输线接收数据信号。