公开(公告)号：US06384319B1

公开(公告)日：2002-05-07

申请号：US09526067

申请日：2000-03-15

申请人： Toshiaki Sasaki ,  Shinji Fujikake

发明人： Toshiaki Sasaki ,  Shinji Fujikake

IPC分类号： H01L31075

CPC分类号： H01L31/03767 ,  H01L31/075 ,  H01L31/20 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521 ,  Y10S136/29

摘要： The film thickness of a p-type semiconductor was adjusted in order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage. In order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage, it was also shown to be favorable to control acceptor impurity levels in p-type semiconductors. Irradiation conditions of more than 10 hours at 1 SUN or (light intensity [SUN])2×10 or more (time [h])>10 were utilized.

摘要翻译： 调整p型半导体的膜厚以达到最大预照射开路电压的0.85-0.99倍。 为了达到最大预照射开路电压的0.85-0.99倍，还显示有利于控制p型半导体中的受主杂质水平。 在1 SUN或（光强度[SUN]）2×10以上（时间[h]）> 10的情况下使用超过10小时的照射条件。

公开(公告)号：US20060076583A1

公开(公告)日：2006-04-13

申请号：US11219320

申请日：2005-09-02

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L29/80

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US5507881A

公开(公告)日：1996-04-16

申请号：US213717

申请日：1994-03-16

申请人： Porponth Sichanugrist ,  Shinji Fujikake ,  Hiromitsu Ota

发明人： Porponth Sichanugrist ,  Shinji Fujikake ,  Hiromitsu Ota

IPC分类号： H01L31/0376 ,  H01L31/075 ,  H01L31/20

CPC分类号： H01L31/20 ,  H01L31/0376 ,  H01L31/075 ,  Y02E10/548

摘要： Solar cells are formed of (a) a transparent substrate; (b) a transparent electrode; (c) a first doped layer comprising amorphous silicon oxide, optionally including nitrogen, said first doped layer containing a dopant whereby the first doped layer is of a first conductivity type and has an optical gap of from 2.0 to 2.3 eV and a ratio of light conductivity to dark conductivity of 5 or less at 25.degree. C.; (d) a layer of intrinsic amorphous silicon; (e) a second doped layer comprising amorphous silicon, said second doped layer containing a dopant whereby the second doped layer is of a second conductivity type different from the first conductivity type; and (f) a second electrode. The first doped layer may be of either n-type or p-type conductivity. The first doped layer can be formed over the transparent electrode by decomposing a gas mixture comprising SiH.sub.4, an oxygen source gas selected from N.sub.2 O or CO.sub.2, and a dopant, in a hydrogen carrier at a substrate temperature of 150.degree. to 250.degree. C., the amount of hydrogen being from 10 to 50 times the amount of SiH.sub.4, said first doped layer being of a first conductivity type. An interfacial layer of intermediate gap may also be included when the first doped layer is a p-type layer. Also described is a method for the formation of an amorphous silicon-oxide film to be utilized in making the thin-film solar cell.

摘要翻译： 太阳能电池由（a）透明基板形成; （b）透明电极; （c）包括非晶氧化硅的第一掺杂层，任选地包括氮，所述第一掺杂层含有掺杂剂，由此所述第一掺杂层是第一导电类型并且具有2.0至2.3eV的光学间隙和光的比率 电导率至25℃的5或更小的暗电导率。 （d）本征非晶硅层; （e）包含非晶硅的第二掺杂层，所述第二掺杂层含有掺杂剂，由此所述第二掺杂层是不同于所述第一导电类型的第二导电类型; 和（f）第二电极。 第一掺杂层可以是n型或p型导电性。 可以在150〜250℃的基板温度下，在氢载体中分解包含SiH 4，选自N 2 O或CO 2的氧源气体和掺杂剂的气体混合物，在透明电极上形成第一掺杂层， 氢的量为SiH4的10至50倍，所述第一掺杂层为第一导电型。 当第一掺杂层是p型层时，也可以包括中间间隙的界面层。 还描述了用于形成用于制造薄膜太阳能电池的非晶氧化硅膜的方法。

公开(公告)号：US07790519B2

公开(公告)日：2010-09-07

申请号：US11754751

申请日：2007-05-29

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/332

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US20070224769A1

公开(公告)日：2007-09-27

申请号：US11754751

申请日：2007-05-29

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/331

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US08664512B2

公开(公告)日：2014-03-04

申请号：US13316157

申请日：2011-12-09

申请人： Makoto Shimosawa ,  Shinji Fujikake ,  Hiroki Sato

发明人： Makoto Shimosawa ,  Shinji Fujikake ,  Hiroki Sato

IPC分类号： H02N6/00 ,  H01L31/042 ,  H01L27/14 ,  H01L27/142 ,  H01L27/144 ,  H01L27/146 ,  H01L51/42

CPC分类号： H01L31/022441 ,  H01L31/044 ,  H01L31/0443 ,  H01L31/0516 ,  Y02E10/50

摘要： The present invention provides a photovoltaic module with bypass diodes that has a high electricity generating capacity per unit area and high productivity. This photovoltaic module includes a photovoltaic cell assembly in which a plurality of photovoltaic cells are electrically connected in series, and a diode assembly in which a plurality of diodes are formed on a substrate in the arrangement that is consistent with the arrangement of the photovoltaic cells to which the diodes are to be attached. The diode assembly is disposed on a non-light receiving side of the photovoltaic cells, and the diodes are electrically connected to the photovoltaic cells. The photovoltaic cell assembly and the diode assembly are sealed and united by a sealant.

摘要翻译： 本发明提供一种具有旁路二极管的光伏模块，其具有高的单位面积发电量和高生产率。 该光伏模块包括其中多个光伏电池串联电连接的光伏电池组件和二极管组件，其中在基板上形成多个二极管，其结构与光伏电池的布置一致 二极管将被连接。 二极管组件设置在光伏电池的非光接收侧，并且二极管电连接到光伏电池。 光伏电池组件和二极管组件通过密封剂密封并结合。

公开(公告)号：US07262100B2

公开(公告)日：2007-08-28

申请号：US11219320

申请日：2005-09-02

申请人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

发明人： Setsuko Wakimoto ,  Manabu Takei ,  Shinji Fujikake

IPC分类号： H01L21/336

CPC分类号： H01L29/1095 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

摘要翻译： 半导体器件具有MOS栅极侧表面结构，其包括填充形成在半导体衬底中的沟槽的栅电极，其中沟槽和栅电极之间具有绝缘膜，覆盖栅电极表面的栅极绝缘膜，缓冲区 与半导体衬底接触的一种导电类型，与栅极绝缘体膜上的缓冲区相邻的另一导电类型的基极区域和与该半导体衬底的相反侧的基极区域相邻的一种导电类型的发射极区域 缓冲区。 半导体器件及其制造方法可以通过增加从表面上的阴极注入的电子量来进一步提高导通电压和关断损耗之间的权衡，以增加阴极侧的载流子的量 稳定的开机状态。

公开(公告)号：US07446889B2

公开(公告)日：2008-11-04

申请号：US11055619

申请日：2005-02-11

申请人： Shinji Fujikake

发明人： Shinji Fujikake

IPC分类号： G01B11/28

CPC分类号： B24B37/013 ,  B24B49/12 ,  H01L21/31053

摘要： A method of evaluating a thickness of a film during a polishing process includes the steps of irradiating light onto a surface of the film during the polishing process; obtaining a differential signal of reflection spectra at a polishing time t and a polishing time t−Δt with a time difference Δt from the polishing time t; and analyzing the differential signal to obtain a thickness d of the film at the polishing time t.

摘要翻译： 在研磨过程中评估膜的厚度的方法包括在抛光过程中将光照射到膜的表面上的步骤; 在抛光时间t和抛光时间t的时间差Δttat处获得反射光谱的差分信号和抛光时间t-Deltat; 并且分析差分信号以获得在抛光时间t的膜的厚度d。

公开(公告)号：US20050191859A1

公开(公告)日：2005-09-01

申请号：US11055619

申请日：2005-02-11

申请人： Shinji Fujikake

发明人： Shinji Fujikake

IPC分类号： B24B49/02 ,  B24B37/013 ,  B24B49/12 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/4763

CPC分类号： B24B37/013 ,  B24B49/12 ,  H01L21/31053

摘要： A method of evaluating a thickness of a film during a polishing process includes the steps of irradiating light onto a surface of the film during the polishing process; obtaining a differential signal of reflection spectra at a polishing time t and a polishing time t−Δt with a time difference Δt from the polishing time t; and analyzing the differential signal to obtain a thickness d of the film at the polishing time t.

摘要翻译： 在研磨过程中评估膜的厚度的方法包括在抛光过程中将光照射到膜的表面上的步骤; 在抛光时间t和抛光时间t的时间差Δttat处获得反射光谱的差分信号和抛光时间t-Deltat; 并且分析差分信号以获得在抛光时间t的膜的厚度d。