公开(公告)号：US20210296300A1

公开(公告)日：2021-09-23

申请号：US17342748

申请日：2021-06-09

Applicant: Toshiba Memory Corporation

Inventor： Hayato MASUBUCHI ,  Naoki KIMURA ,  Manabu MATSUMOTO ,  Toyota MORIMOTO

IPC: H01L25/18 ,  H05K1/02 ,  H05K3/30 ,  H01L23/498 ,  H01L27/115 ,  G11C5/02 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/528 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20200301495A1

公开(公告)日：2020-09-24

申请号：US16549464

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hayato MASUBUCHI

IPC: G06F1/28 ,  G11C16/30 ,  G11C16/10 ,  G11C14/00

Abstract: An electronic device includes a power supply circuit, a first counter that counts the number of times that supply of external power to the power supply circuit is stopped, a second counter that is operated by a first power and counts the number of times that generation of the plurality of kinds of power is stopped, a third counter counting the number of times that any of the plurality of kinds of power is dropped to a predetermined voltage or less, a non-volatile first memory storing status information indicating whether or not supply of the external power to the power supply circuit is properly stopped, and a fourth counter that counts the number of times that the supply of the external power to the power supply circuit is properly stopped and the number of times that the supply of the external power to the power supply circuit is abnormally stopped.

公开(公告)号：US20190326275A1

公开(公告)日：2019-10-24

申请号：US16502288

申请日：2019-07-03

Applicant: Toshiba Memory Corporation

Inventor： Hayato MASUBUCHI ,  Naoki KIMURA ,  Manabu MATSUMOTO ,  Toyota MORIMOTO

IPC: H01L25/18 ,  H01L25/00 ,  H05K1/02 ,  H05K3/30 ,  H01L23/498 ,  H01L27/115 ,  H01L23/528 ,  H05K1/18 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  G11C5/02

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20180076186A1

公开(公告)日：2018-03-15

申请号：US15822039

申请日：2017-11-24

Applicant: Toshiba Memory Corporation

Inventor： Hayato MASUBUCHI ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC: H01L25/18 ,  H05K1/02 ,  H05K3/30 ,  H01L23/528 ,  H01L23/498 ,  H01L25/00 ,  H01L27/115

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/115 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20200034068A1

公开(公告)日：2020-01-30

申请号：US16352021

申请日：2019-03-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hayato MASUBUCHI

IPC: G06F3/06 ,  G11C16/30 ,  G01K3/10 ,  G01K1/02

Abstract: According to one embodiment, a controller acquires temperature data periodically while receiving a first mode designating signal, writes the temperature data into a nonvolatile storage while or after the first mode designating signal, acquires temperature data after a lapse of a predetermined time from designation of the second mode, writes the temperature data into the nonvolatile storage while or after a lapse of a predetermined time since the designation of the second mode, acquires temperature data at a timing of changing from the second mode to the first mode, and write the acquired temperature data into the nonvolatile storage at or after the timing of changing from the second mode to the first mode.