公开(公告)号：US20180269228A1

公开(公告)日：2018-09-20

申请号：US15980966

申请日：2018-05-16

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SONEHARA ,  Masaru KITO

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.

公开(公告)号：US20190148404A1

公开(公告)日：2019-05-16

申请号：US16245271

申请日：2019-01-11

Applicant: Toshiba Memory Corporation

Inventor： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/115 ,  H01L27/105 ,  H01L27/06 ,  H01L21/822

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20180175057A1

公开(公告)日：2018-06-21

申请号：US15897623

申请日：2018-02-15

Applicant: Toshiba Memory Corporation

Inventor： Masaaki HIGUCHI ,  Masaru KITO ,  Masao SHINGU

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

公开(公告)号：US20200075625A1

公开(公告)日：2020-03-05

申请号：US16293954

申请日：2019-03-06

Applicant: Toshiba Memory Corporation

Inventor： Shigeki KOBAYASHI ,  Masaru KITO ,  Yasuhiro UCHIYAMA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

公开(公告)号：US20190296040A1

公开(公告)日：2019-09-26

申请号：US16122258

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Masahisa SONODA ,  Masaru KITO ,  Satoshi NAGASHIMA ,  Shigeki KOBAYASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08

Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.

公开(公告)号：US20180240814A1

公开(公告)日：2018-08-23

申请号：US15960842

申请日：2018-04-24

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20200303408A1

公开(公告)日：2020-09-24

申请号：US16570067

申请日：2019-09-13

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yuji SETTA ,  Masaru KITO

IPC: H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11573 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

公开(公告)号：US20180175048A1

公开(公告)日：2018-06-21

申请号：US15883730

申请日：2018-01-30

Applicant: Toshiba Memory Corporation

Inventor： Naoki YASUDA ,  Masaru KITO

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11568

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.