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公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译： 半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。
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公开(公告)号：US20060266996A1
公开(公告)日：2006-11-30
申请号：US11437730
申请日：2006-05-22
IPC分类号： H01L31/00
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
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公开(公告)号：US20070241399A1
公开(公告)日：2007-10-18
申请号：US11705450
申请日：2007-02-13
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译： 在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极， 并且源极/漏极形成为与半导体层接触。 半导体层具有沿给定方向的多个侧表面。 由相邻侧面形成的所有角度大于90°。 垂直于给定方向的部分垂直和水平对称。
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4.发明授权Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor 有权包括多栅极金属 - 绝缘体 - 半导体（MIS）晶体管的半导体器件公开(公告)号：US07622773B2
公开(公告)日：2009-11-24
申请号：US11705450
申请日：2007-02-13
IPC分类号： H01L27/12
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译： 在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极， 并且源极/漏极形成为与半导体层接触。 半导体层具有沿给定方向的多个侧表面。 由相邻侧面形成的所有角度大于90°。 垂直于给定方向的部分垂直和水平对称。
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公开(公告)号：US20080135886A1
公开(公告)日：2008-06-12
申请号：US11950716
申请日：2007-12-05
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译： 半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。
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公开(公告)号：US20110147805A1
公开(公告)日：2011-06-23
申请号：US13037049
申请日：2011-02-28
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译： 半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在沟道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。
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公开(公告)号：US08174095B2
公开(公告)日：2012-05-08
申请号：US13037049
申请日：2011-02-28
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译： 半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。
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公开(公告)号：US08008751B2
公开(公告)日：2011-08-30
申请号：US11950716
申请日：2007-12-05
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译： 半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。
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公开(公告)号：US06917096B2
公开(公告)日：2005-07-12
申请号：US10611157
申请日：2003-07-02
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/84 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/786 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译： 半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层 形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道， 以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。
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公开(公告)号：US06607948B1
公开(公告)日：2003-08-19
申请号：US09935685
申请日：2001-08-24
IPC分类号： H01L2184
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译： 半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层 形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道， 以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。
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