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公开(公告)号：US06917096B2
公开(公告)日：2005-07-12
申请号：US10611157
申请日：2003-07-02
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/84 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/786 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译： 半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层 形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道， 以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。
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公开(公告)号：US06607948B1
公开(公告)日：2003-08-19
申请号：US09935685
申请日：2001-08-24
IPC分类号： H01L2184
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译： 半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层 形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道， 以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。
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公开(公告)号：US06326667B1
公开(公告)日：2001-12-04
申请号：US09658191
申请日：2000-09-08
IPC分类号： H01L2972
CPC分类号： H01L29/66916 , H01L29/78687 , H01L29/802
摘要： The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer 13 is formed on a Si substrate 11 and an oxygen ion implantation is effected with ensuring the detainment within the layer thickness of the SiGe layer 13. The SiGe layer 13 is lattice-relaxed by a heat treatment and a buried insulating layer 15 is formed simultaneously in the SiGe layer 13. A strained Si layer 17 is re-grown on the lattice-relaxed SiGe layer 13.
摘要翻译： 本发明旨在在绝缘层上形成用作获得应变硅层的下层的薄SiGe层，并提供令人满意的应变Si层。 在Si衬底11上形成SiGe层13，并且确保在SiGe层13的层厚度内保留的氧离子注入。通过热处理和掩埋绝缘层15对SiGe层13进行晶格弛豫 在SiGe层13中同时形成。应变Si层17在晶格弛豫SiGe层13上重新生长。
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公开(公告)号：US06774390B2
公开(公告)日：2004-08-10
申请号：US10369662
申请日：2003-02-21
IPC分类号： H01L2906
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/7378 , H01L29/78687
摘要： A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.
摘要翻译： 半导体器件包括绝缘层，形成在绝缘层的选定部分上的半导体板，形成在晶格常数不同于半导体板的半导体板的至少一个主侧面上的半导体层， 并且其间具有源极和漏极区域和沟道区域，沟道区域的面积大于与绝缘层接触的半导体板的底表面的面积，以及通过栅绝缘形成在沟道区域上的栅电极 层。
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公开(公告)号：US06509587B2
公开(公告)日：2003-01-21
申请号：US09955144
申请日：2001-09-19
IPC分类号： H01L350328
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.
摘要翻译： 诸如具有应变Si沟道和异质双极晶体管的场效应晶体管的高速和低功耗晶体管彼此集成。 这里使用的是这样的复杂结构，其中具有薄膜SiGe缓冲层和应变Si沟道的MOSFET层叠在绝缘膜上，并且通过外延生长在薄膜SiGe层上形成具有SiGe基层的HBT， 形成在SiGe基底层上的Si发射极层彼此结合。 在MOSFET的绝缘膜上形成的薄膜SiGe层比HBT的对应物薄。 在MOSFET的绝缘膜上形成的薄膜SiGe层的Ge浓度高于HBT的绝缘膜。
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6.发明授权Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same 失效具有多层IV族纳米晶体量子点浮栅的半导体存储器件及其制造方法
公开(公告)号：US6060743A
公开(公告)日：2000-05-09
申请号：US82613
申请日：1998-05-20
IPC分类号： H01L29/788 , H01L21/336 , H01L29/06 , H01L29/15
CPC分类号： B82Y10/00 , H01L29/7883 , H01L29/7888 , Y10S438/962
摘要： The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.
摘要翻译： 所述半导体器件包括形成在所述半导体衬底上的第一绝缘层，形成在所述第一绝缘层上的至少一个双层半导体纳米晶体，所述至少一个双层半导体纳米晶体包括第一半导体纳米晶体和第二半导体纳米晶体， 另一方面通过第二绝缘层，以及选择性地形成在第一绝缘层上以覆盖至少一个双层半导体纳米晶体的第三绝缘层。
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公开(公告)号：US5847419A
公开(公告)日：1998-12-08
申请号：US931411
申请日：1997-09-16
IPC分类号： H01L27/06 , H01L27/092 , H01L29/786 , H01L29/161
CPC分类号： H01L29/78654 , H01L27/0605 , H01L27/0688 , H01L27/0922
摘要： A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.
摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的压缩应变下的第一半导体层，形成在第一半导体层的预定区域中的p型MISFET（金属绝缘体半导体场效应晶体管），第二半导体层 形成在第一半导体层上的除了预定区域之外的区域中的绝缘膜的晶格弛豫状态，其中绝缘膜具有开口，并且第一和第二半导体层通过开口连接，第三半导体层 在第二半导体层上形成的拉伸应变下，形成在第三半导体层中的n型MISFET（金属绝缘子半导体场效应晶体管）。
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公开(公告)号：US06709909B2
公开(公告)日：2004-03-23
申请号：US10440133
申请日：2003-05-19
IPC分类号： H01L21338
CPC分类号： H01L21/76243 , H01L21/26533 , H01L29/1054 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.
摘要翻译： 一种制造半导体器件的方法，包括：通过将氧离子注入到第一SiGe层中形成具有低Ge含量的第一SiGe层，形成氧化层，然后退火第一SiGe层。 该方法还包括在第一SiGe层上形成第二SiGe层，其具有比第一SiGe层更高的Ge含量，在第二SiGe层上形成应变Si层，并形成其中应变的场效晶体管 Si层用于沟道区。 此外，可以在具有不可缺的，高质量的掩埋氧化物层和大的应变Si层的半导体衬底上形成场效应晶体管，因此可以实现高速，低功耗的半导体器件。
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公开(公告)号：US06583437B2
公开(公告)日：2003-06-24
申请号：US09810607
申请日：2001-03-19
IPC分类号： H01L310328
CPC分类号： H01L21/76243 , H01L21/26533 , H01L29/1054 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.
摘要翻译： 一种制造半导体器件的方法，包括：通过将氧离子注入到第一SiGe层中形成具有低Ge含量的第一SiGe层，形成氧化层，然后退火第一SiGe层。 该方法还包括在第一SiGe层上形成第二SiGe层，其具有比第一SiGe层更高的Ge含量，在第二SiGe层上形成应变Si层，并形成其中应变的场效晶体管 Si层用于沟道区。 此外，可以在具有不可缺的，高质量的掩埋氧化物层和大的应变Si层的半导体衬底上形成场效应晶体管，因此可以实现高速，低功耗的半导体器件。
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公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译： 半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。
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