公开(公告)号：US20050227498A1

公开(公告)日：2005-10-13

申请号：US10814482

申请日：2004-03-31

申请人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

发明人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/469

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US20050087875A1

公开(公告)日：2005-04-28

申请号：US10605766

申请日：2003-10-24

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wiring-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

摘要翻译： 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在布线层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US20080050931A1

公开(公告)日：2008-02-28

申请号：US11926613

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

发明人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

IPC分类号： H01L21/31

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US20060060562A1

公开(公告)日：2006-03-23

申请号：US10711458

申请日：2004-09-20

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC分类号： C23F1/00 ,  B44C1/22 ,  G03C5/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.

摘要翻译： 提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。 在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。 例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。 另一个边缘被记住在图层中。 去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

公开(公告)号：US20080157202A1

公开(公告)日：2008-07-03

申请号：US11618346

申请日：2006-12-29

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

公开(公告)号：US20080099844A1

公开(公告)日：2008-05-01

申请号：US11969320

申请日：2008-01-04

申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

IPC分类号： H01L29/786

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

摘要翻译： 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。

公开(公告)号：US20080001225A1

公开(公告)日：2008-01-03

申请号：US11307294

申请日：2006-01-31

申请人： Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US20070241409A1

公开(公告)日：2007-10-18

申请号：US11764571

申请日：2007-06-18

申请人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76237 ,  H01L21/26533 ,  H01L21/76213 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。 成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。 也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

公开(公告)号：US20070241408A1

公开(公告)日：2007-10-18

申请号：US11759981

申请日：2007-06-08

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

公开(公告)号：US20070215874A1

公开(公告)日：2007-09-20

申请号：US11378492

申请日：2006-03-17

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

IPC分类号： H01L23/58

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

摘要翻译： 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。