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公开(公告)号：US07081387B2
公开(公告)日：2006-07-25
申请号：US10918949
申请日：2004-08-16
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
摘要翻译： 公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。 在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法，例如气相掺杂或等离子体掺杂时。 所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。 提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。
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公开(公告)号：US06818952B2
公开(公告)日：2004-11-16
申请号：US10262190
申请日：2002-10-01
IPC分类号： H01L2701
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
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公开(公告)号：US06635543B2
公开(公告)日：2003-10-21
申请号：US10335652
申请日：2002-12-31
IPC分类号： A01L21331
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.
摘要翻译： 一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。 衬垫层形成在硅层上。 焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。 通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。 绝缘垫片形成在沟槽的侧壁上。 在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。 去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。 电子器件可以形成在沟槽的外延硅内。 这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。 半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。
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公开(公告)号：US06555891B1
公开(公告)日：2003-04-29
申请号：US09690674
申请日：2000-10-17
IPC分类号： H01L2900
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.
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公开(公告)号：US06509611B1
公开(公告)日：2003-01-21
申请号：US09961010
申请日：2001-09-21
IPC分类号： H01L2994
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66545 , H01L29/66795 , H01L29/78618
摘要： A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the “body-to-source” voltage.
摘要翻译： 包裹栅极晶体管包括具有上表面和彼此相对的第一和第二侧表面的衬底。 源极和漏极区域形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 在基板上形成栅介电层。 栅极电极形成在栅极电介质层上，以覆盖来自上表面和第一和第二侧表面的沟道区域，栅电介质在其间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛，并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。
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公开(公告)号：US20050012145A1
公开(公告)日：2005-01-20
申请号：US10918949
申请日：2004-08-16
IPC分类号： H01L29/423 , H01L21/265 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
摘要翻译： 公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。 在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法，例如气相掺杂或等离子体掺杂时。 所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。 提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。
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公开(公告)号：US20120129319A1
公开(公告)日：2012-05-24
申请号：US13362043
申请日：2012-01-31
申请人： Alberto Cestero , Byeongju Park , John M. Safran
发明人： Alberto Cestero , Byeongju Park , John M. Safran
IPC分类号： H01L21/326
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.
摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。
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公开(公告)号：US07674691B2
公开(公告)日：2010-03-09
申请号：US11683068
申请日：2007-03-07
申请人： Alberto Cestero , Byeongju Park , John M. Safran
发明人： Alberto Cestero , Byeongju Park , John M. Safran
IPC分类号： H01L21/326
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.
摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。
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9.发明申请ANTI-FUSE STRUCTURE INCLUDING A SENSE PAD CONTACT REGION AND METHODS FOR FABRICATION AND PROGRAMMING THEREOF 审中-公开包括感应接头接触区域的防冻结构及其制造和编程方法公开(公告)号：US20090108400A1
公开(公告)日：2009-04-30
申请号：US11931167
申请日：2007-10-31
申请人： Alberto Cestero , Byeongju Park , John Safran
发明人： Alberto Cestero , Byeongju Park , John Safran
IPC分类号： H01L23/58 , H01L21/441
CPC分类号： H01L23/5252 , H01L23/58 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse structure may travel a different pathway than a sense current flow when sensing the antifuse structure. In particular a sense current flow may avoid a depletion region created within the cathode contact region when programming the antifuse structure.
摘要翻译： 反熔丝结构包括与阳极接触区域和阴极接触区域分开的感测焊盘接触区域。 通过包括与阳极接触区域和阴极接触区域分开的感测焊盘接触区域，编程反熔丝结构时的编程电流将在检测反熔丝结构时传播与感测电流不同的通路。 特别地，当编程反熔丝结构时，感测电流可以避免在阴极接触区域内产生的耗尽区域。
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10.发明申请PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL 有权使用外部加热相变材料在BEOL区域可编程保险丝/非易失性存储器结构公开(公告)号：US20090065761A1
公开(公告)日：2009-03-12
申请号：US11850742
申请日：2007-09-06
申请人： Kuang-Neng Chen , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Chung Hon Lam , Lia Krusin-Elbaum , Dennis M. Newns , Byeongju Park , Sampath Purushothaman
发明人： Kuang-Neng Chen , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Chung Hon Lam , Lia Krusin-Elbaum , Dennis M. Newns , Byeongju Park , Sampath Purushothaman
CPC分类号： H01L23/5256 , H01L27/2436 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.
摘要翻译： 可编程相变材料（PCM）结构包括形成在半导体器件的BEOL级的加热器元件，BEOL级包括其中的低K电介质材料; 与加热器元件的第一端电接触的第一通孔和与加热器元件的第二端电接触的第二通孔，从而限定通过第一通孔，加热元件和第二通孔的编程电流通路 通过; 设置在所述加热器元件上方的PCM元件，所述PCM元件被配置为通过使用通过所述加热器元件的编程电流在较低电阻结晶状态和较高电阻非晶态之间被编程; 以及与PCM元件电接触的第三通孔，从而限定穿过第三通孔，PCM元件，加热器元件和第二通孔的感测电流路径。
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