公开(公告)号：US06555891B1

公开(公告)日：2003-04-29

申请号：US09690674

申请日：2000-10-17

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： H01L2900

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

公开(公告)号：US06509611B1

公开(公告)日：2003-01-21

申请号：US09961010

申请日：2001-09-21

申请人： Byeongju Park ,  Toshiharu Furukawa ,  Jack A. Mandelman

发明人： Byeongju Park ,  Toshiharu Furukawa ,  Jack A. Mandelman

IPC分类号： H01L2994

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

摘要： A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the “body-to-source” voltage.

摘要翻译： 包裹栅极晶体管包括具有上表面和彼此相对的第一和第二侧表面的衬底。 源极和漏极区域形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 在基板上形成栅介电层。 栅极电极形成在栅极电介质层上，以覆盖来自上表面和第一和第二侧表面的沟道区域，栅电介质在其间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛，并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

公开(公告)号：US07081387B2

公开(公告)日：2006-07-25

申请号：US10918949

申请日：2004-08-16

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

摘要翻译： 公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。 在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法，例如气相掺杂或等离子体掺杂时。 所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。 提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。

公开(公告)号：US06818952B2

公开(公告)日：2004-11-16

申请号：US10262190

申请日：2002-10-01

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

IPC分类号： H01L2701

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

公开(公告)号：US06635543B2

公开(公告)日：2003-10-21

申请号：US10335652

申请日：2002-12-31

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： A01L21331

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

摘要翻译： 一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。 衬垫层形成在硅层上。 焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。 通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。 绝缘垫片形成在沟槽的侧壁上。 在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。 去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。 电子器件可以形成在沟槽的外延硅内。 这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。 半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

公开(公告)号：US20080157202A1

公开(公告)日：2008-07-03

申请号：US11618346

申请日：2006-12-29

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

公开(公告)号：US06380027B2

公开(公告)日：2002-04-30

申请号：US09225127

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

发明人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

IPC分类号： H01L21242

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10894

摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

摘要翻译： 用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及 其中所述第一氧化物比所述第二氧化物厚。

公开(公告)号：US6114725A

公开(公告)日：2000-09-05

申请号：US93928

申请日：1998-06-09

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US07521776B2

公开(公告)日：2009-04-21

申请号：US11618346

申请日：2006-12-29

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

公开(公告)号：US06396120B1

公开(公告)日：2002-05-28

申请号：US09527191

申请日：2000-03-17

申请人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

发明人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

IPC分类号： H01L2972

CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823456 ,  H01L23/5252 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.

摘要翻译： 一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。 半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域 在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。 在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏 电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给 所述基板。