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186 条记录 (耗时 0.043 秒)

    Structure for folded architecture pillar memory cell
    7.
    发明授权
    Structure for folded architecture pillar memory cell 有权
    折叠式立柱式记忆体结构

    公开(公告)号：US06440801B1

    公开(公告)日：2002-08-27

    申请号：US09604901

    申请日：2000-06-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    IPC分类号： H01L21336

    CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

    摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

    摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

    DRAM cell with grooved transfer device
    8.
    发明授权
    DRAM cell with grooved transfer device 失效
    具有槽式转移装置的DRAM单元

    公开(公告)号：US5945707A

    公开(公告)日：1999-08-31

    申请号：US56903

    申请日：1998-04-07

    申请人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

    发明人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

    IPC分类号： H01L21/8242 ,  H01L29/72

    CPC分类号： H01L27/10876 ,  H01L27/10861 ,  H01L27/10891

    摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

    摘要翻译： 公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。 凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。 沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。 因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。 沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

    Process for making a DRAM cell with three-sided gate transfer
    9.
    发明授权
    Process for making a DRAM cell with three-sided gate transfer 失效
    用于制造具有三面栅极转移的DRAM单元的工艺

    公开(公告)号：US06323082B1

    公开(公告)日：2001-11-27

    申请号：US09565504

    申请日：2000-05-05

    申请人： Toshiharu Furukawa ,  David V. Horak ,  Steven J. Holmes ,  Mark C. Hakey ,  Jack A. Mandelman

    发明人： Toshiharu Furukawa ,  David V. Horak ,  Steven J. Holmes ,  Mark C. Hakey ,  Jack A. Mandelman

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/7851 ,  Y10S257/906 ,  Y10S438/947

    摘要： A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.

    摘要翻译： DRAM装置和制造装置的过程。 DRAM装置包括通过由字线控制的传送装置耦合到信号存储节点的位线。 转印装置包括具有第一端，与第一端相对的第二端，顶部，第一侧和与第一侧相对的第二侧的台面结构。 位线扩散区域将台面结构的第一端耦合到位线接触。 存储节点扩散区将台面结构的第二端耦合到信号存储节点。 字线通过形成在台面结构的第一面，第二面和顶部上的栅极来控制形成在台面结构中的通道。 台面结构的亚最小宽度允许容易地实现完全耗尽，导致通道中的体积反转。

    Dram cell with three-sided-gate transfer device
    10.
    发明授权
    Dram cell with three-sided-gate transfer device 失效
    具有三边门转移装置的电池

    公开(公告)号：US6121651A

    公开(公告)日：2000-09-19

    申请号：US126412

    申请日：1998-07-30

    申请人： Toshiharu Furukawa ,  David V. Horak ,  Steven J. Holmes ,  Mark C. Hakey ,  Jack A. Mandelman

    发明人： Toshiharu Furukawa ,  David V. Horak ,  Steven J. Holmes ,  Mark C. Hakey ,  Jack A. Mandelman

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/10829 ,  H01L29/7851 ,  Y10S257/906 ,  Y10S438/947

    摘要： A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.

    摘要翻译： DRAM装置和制造装置的过程。 DRAM装置包括通过由字线控制的传送装置耦合到信号存储节点的位线。 转印装置包括具有第一端，与第一端相对的第二端，顶部，第一侧和与第一侧相对的第二侧的台面结构。 位线扩散区域将台面结构的第一端耦合到位线接触。 存储节点扩散区将台面结构的第二端耦合到信号存储节点。 字线通过形成在台面结构的第一面，第二面和顶部上的栅极来控制形成在台面结构中的通道。 台面结构的亚最小宽度允许容易地实现完全耗尽，导致通道中的体积反转。