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    Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer
    8.
    发明授权
    Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer 失效
    使用锗氧化物牺牲层将掺杂剂引入半导体器件的方法

    公开(公告)号：US06333245B1

    公开(公告)日：2001-12-25

    申请号：US09469137

    申请日：1999-12-21

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Donald W. Rakowski

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Donald W. Rakowski

    IPC分类号： H01L2122

    CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842

    摘要： A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.

    摘要翻译： 公开了一种使用掺杂的氧化锗将掺杂剂引入半导体器件的方法。 该方法包括使用快速热退火（RTA）或炉退火来从半导体衬底上的掺杂的锗氧化物牺牲层将掺杂剂扩散到衬底中。 退火之后将掺杂剂扩散到衬底中，使用水去除锗氧化物牺牲层，从而避免在栅极或标准器件隔离结构中去除二氧化硅（SiO 2），这可能导致器件故障。 N +和p +源极和漏极可以在半导体衬底中的适当的阱中使用单一退火形成，并且不需要限定第一掺杂牺牲层的不止一个区域。 或者，在将第二掺杂剂引入到氧化锗牺牲层中之前的退火给出较慢的扩散离子，例如砷开始。

    Method of manufacturing dual gate logic devices
    10.
    发明授权
    Method of manufacturing dual gate logic devices 失效
    制造双门逻辑器件的方法

    公开(公告)号：US06596597B2

    公开(公告)日：2003-07-22

    申请号：US09879590

    申请日：2001-06-12

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    IPC分类号： H01L21336

    CPC分类号： H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

    摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

    摘要翻译： 本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在电介质壳体中而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。