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    Method of making a through hole in multi-layer insulating films
    3.
    发明授权
    Method of making a through hole in multi-layer insulating films 失效
    在多层绝缘膜中制作通孔的方法

    公开(公告)号：US5378652A

    公开(公告)日：1995-01-03

    申请号：US680781

    申请日：1991-04-03

    申请人： Shuichi Samata ,  Yuuichi Mikata ,  Toshiro Usami

    发明人： Shuichi Samata ,  Yuuichi Mikata ,  Toshiro Usami

    IPC分类号： H01L21/285 ,  H01L23/532 ,  H01L29/417 ,  H01L29/45 ,  H01L29/54 ,  H01L21/20

    CPC分类号： H01L21/28525 ,  H01L23/5329 ,  H01L29/41725 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/971

    摘要： A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

    摘要翻译： 具有电极布线结构的半导体器件包括设置在半导体衬底中的至少一个扩散区域，覆盖衬底表面的氧化硅层，设置在氧化硅层上的氮化硅层，通过所述扩散区域的通孔 从氮化硅层的上表面的氧化硅层，填充在通孔中并用作电极布线层的硅半导体层，以及通过硅半导体层与扩散区电连接的布线层。 根据该结构，由于氧化硅层被氮化硅层覆盖，因此在硅生长过程中，硅氧化物层中预先含有的诸如磷，硼等的不需要的污染物不会添加到硅半导体层。 因此，可以提供具有受控导电性的硅半导体的电极布线层。

    Semiconductor device silicon via fill formed in multiple dielectric layers
    5.
    发明授权
    Semiconductor device silicon via fill formed in multiple dielectric layers 失效
    半导体器件硅通孔填充物形成在多个电介质层中

    公开(公告)号：US5291058A

    公开(公告)日：1994-03-01

    申请号：US921685

    申请日：1992-07-30

    申请人： Shuichi Samata ,  Yuuichi Mikata ,  Toshiro Usami

    发明人： Shuichi Samata ,  Yuuichi Mikata ,  Toshiro Usami

    IPC分类号： H01L21/285 ,  H01L23/532 ,  H01L29/417 ,  H01L29/45 ,  H01L29/34 ,  H01L21/225 ,  H01L23/48 ,  H01L29/46

    CPC分类号： H01L21/28525 ,  H01L23/5329 ,  H01L29/41725 ,  H01L29/456 ,  H01L2924/0002

    摘要： A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

    摘要翻译： 具有电极布线结构的半导体器件包括设置在半导体衬底中的至少一个扩散区域，覆盖衬底表面的氧化硅层，设置在氧化硅层上的氮化硅层，通过所述扩散区域的通孔 从氮化硅层的上表面的氧化硅层，填充在通孔中并用作电极布线层的硅半导体层，以及通过硅半导体层与扩散区电连接的布线层。 根据该结构，由于氧化硅层被氮化硅层覆盖，因此在硅生长过程中，硅氧化物层中预先含有的诸如磷，硼等的不需要的污染物不会添加到硅半导体层。 因此，可以提供具有受控导电性的硅半导体的电极布线层。

    Method for manufacturing semiconductor device having gate electrodes of different conductivity types
    6.
    发明授权
    Method for manufacturing semiconductor device having gate electrodes of different conductivity types 失效
    具有不同导电类型的栅电极的半导体器件的制造方法

    公开(公告)号：US4966866A

    公开(公告)日：1990-10-30

    申请号：US399213

    申请日：1989-08-29

    申请人： Yuuichi Mikata ,  Shuichi Samata

    发明人： Yuuichi Mikata ,  Shuichi Samata

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

    CPC分类号： H01L29/4916 ,  H01L21/28035 ,  H01L21/823842 ,  H01L27/0925 ,  H01L29/4925

    摘要： Disclosed is a method for manufacturing a semiconductor device, for example, an MOSFET. According to this method, an n-well region is formed in a predetermined portion of a p-type semiconductor substrate, after which a field oxide film is formed on that portion of the n-well region which is in contact with the p-type semiconductor substrate. Next, a gate oxide film is formed on the p-type semiconductor substrate and the n-well region, and when a polycrystal silicon film is formed on the field oxide film and the gate oxide film. Thereafter, a polycrystal silicon film containing boron is formed on that portion of the above polycrystal silicon film formed on the p-channel MOSFET forming region, a polycrystal silicon film containing phosphorus being formed on that portion of the polycrystal film formed on the n-channel MOSFET forming region. The above-mentioned three polycrystal silicon films are then patterned, thereby to form a p-type gate electrode including the polycrystal silicon on the gate oxide electrode and the polycrystal silicon containing boron, and an n-type gate electrode including the polycrystal silicon film on the gate oxide electrode and the polycrystal silicon film containing phosphorus.

    摘要翻译： 公开了一种用于制造例如MOSFET的半导体器件的方法。 根据该方法，在p型半导体衬底的预定部分中形成n阱区，之后在与p-型半导体衬底接触的n阱区的部分上形成场氧化膜 半导体衬底。 接着，在p型半导体衬底和n阱区上形成栅极氧化膜，在场氧化膜和栅极氧化膜上形成多晶硅膜时。 此后，在形成在p沟道MOSFET形成区域上的上述多晶硅膜的部分上形成含有硼的多晶硅膜，在形成于n沟道上的多晶膜部分上形成含有磷的多晶硅膜 MOSFET形成区域。 然后对上述三种多晶硅膜进行构图，从而形成包括在栅极氧化物电极上的多晶硅和含硼多晶硅的p型栅电极，以及包含多晶硅膜的n型栅电极 栅氧化物电极和含磷的多晶硅膜。

    Semiconductor manufacturing line availability evaluating system and design system
    8.
    发明授权
    Semiconductor manufacturing line availability evaluating system and design system 失效
    半导体生产线可用性评估系统和设计系统

    公开(公告)号：US06983191B2

    公开(公告)日：2006-01-03

    申请号：US10948166

    申请日：2004-09-24

    申请人： Yuuichi Mikata

    发明人： Yuuichi Mikata

    IPC分类号： G06F19/00

    CPC分类号： H01L21/67276

    摘要： An availability evaluation system of a semiconductor manufacturing line, comprising a unit configured to calculate an incidence probability Xi (i=1 to k) in combination by applying a tool operation probability and a tool stoppage probability to all combinations “k” in which at least a line fabrication availability is not zero, of the combinations of operation and stoppage of tools, and by obtaining a product of the probabilities of all the tools, and a unit configured to, when a product between the incidence probability Xi of a combination and a fabrication availability Yi of the combination is defined as a probability converted fabrication availability with respect to each of the combinations, calculate an availability value of Q=Σ(i=1 to k)X1×Y1/F obtained by dividing a sum of probability converted fabrication availabilities of the combinations by a fabrication availability F at a 100% availability.

    摘要翻译： 一种半导体生产线的可用性评估系统，包括被配置为通过对所有组合“k”应用工具操作概率和工具停止概率来计算出发概率Xi（i = 1至k）的单元，其中至少 线路制造可用性不是零，工具的操作和停止的组合，以及通过获得所有工具的概率的乘积，以及被配置为当组合的发生概率Xi和 将组合的制造可用性Yi定义为相对于每个组合的概率转换的制造可用性，计算Q =Σ（i = 1至k）X 1 xY 1 / F的可用性值 通过在100％可用性下将制造可用性F除以组合的概率转换制造可用性的总和来获得。

    Semiconductor device applied to composite insulative film and manufacturing method thereof
    9.
    发明授权
    Semiconductor device applied to composite insulative film and manufacturing method thereof 失效
    具有氮化物膜的半导体器件

    公开(公告)号：US5838056A

    公开(公告)日：1998-11-17

    申请号：US777100

    申请日：1996-12-30

    申请人： Yoshio Kasai ,  Takashi Suzuki ,  Takanori Tsuda ,  Yuuichi Mikata ,  Hiroshi Akahori ,  Akihito Yamamoto

    发明人： Yoshio Kasai ,  Takashi Suzuki ,  Takanori Tsuda ,  Yuuichi Mikata ,  Hiroshi Akahori ,  Akihito Yamamoto

    IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/318 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/58

    CPC分类号： H01L29/66181 ,  H01L21/28167 ,  H01L21/3185

    摘要： A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH.sub.3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800.degree. C. to 1200.degree. C. and the partial pressures of H.sub.2 O and O.sub.2 are set at 1.times.10.sup.-4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.

    摘要翻译： 清洁在沟槽的内表面形成有杂质扩散层的半导体晶片。 将半导体晶片插入炉中，并将NH 3气体在低压条件下引入炉中以产生温度设定在800℃至1200℃的气氛，并且将H 2 O和 O2设定在1×10-4乇或更低。 去除形成在沟槽内表面上的自然氧化膜，并且基本上同时在杂质扩散层上形成氮化氮膜。 然后，在氮化硅膜上形成CVD氮化硅膜，而不会在同一炉内将氮化氮膜暴露于外部空气。 接着，在CVD氮化膜上形成氧化硅膜。 结果，得到由氮化物膜，CVD氮化硅膜和氧化硅膜形成的复合绝缘膜。 然后，在沟槽中形成用于复合绝缘膜的电极。

    Method of manufacturing SiO.sub.2 -Si interface for floating gate semiconductor device
    10.
    发明授权
    Method of manufacturing SiO.sub.2 -Si interface for floating gate semiconductor device 失效
    制造浮栅半导体器件的SiO2-Si界面的方法

    公开(公告)号：US4597159A

    公开(公告)日：1986-07-01

    申请号：US706096

    申请日：1985-02-27

    申请人： Toshiro Usami ,  Yuuichi Mikata ,  Kazuyoshi Shinada

    发明人： Toshiro Usami ,  Yuuichi Mikata ,  Kazuyoshi Shinada

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/34 ,  H01L21/76 ,  H01L21/94

    CPC分类号： H01L21/28273 ,  Y10S148/053 ,  Y10S148/138 ,  Y10S148/169

    摘要： A semiconductor device is manufactured by forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type, and a first nonmonocrystalline silicon film is formed on the first insulating film. A second insulating film is deposited on the first nonmonocrystalline silicon film by CVD, sputtering or molecular beam method. An impurity is then ion-implanted in the first nonmonocrystalline silicon film through the second insulating film. The second insulating film is then removed to expose the surface of the first nonmonocrystalline silicon film doped with the impurity, and a thermal oxide film is formed on the exposed portion of the first nonmonocrystalline silicon film. Subsequently, a second nonmonocrystalline silicon film is formed on the thermal oxide film, and a third insulating film is formed on the second nonmonocrystalline silicon film.

    摘要翻译： 通过在第一导电类型的半导体衬底的表面上形成第一绝缘膜，并且在第一绝缘膜上形成第一非单晶硅膜来制造半导体器件。 通过CVD，溅射或分子束方法将第二绝缘膜沉积在第一非单晶硅膜上。 然后通过第二绝缘膜将杂质离子注入到第一非单晶硅膜中。 然后去除第二绝缘膜以暴露掺杂有杂质的第一非单晶硅膜的表面，并且在第一非单晶硅膜的暴露部分上形成热氧化膜。 随后，在热氧化膜上形成第二非单晶硅膜，在第二非单晶硅膜上形成第三绝缘膜。