公开(公告)号：US5649229A

公开(公告)日：1997-07-15

申请号：US419957

申请日：1995-04-10

申请人： Toshimichi Matsuzaki ,  Nobuo Higaki ,  Masashi Deguchi

发明人： Toshimichi Matsuzaki ,  Nobuo Higaki ,  Masashi Deguchi

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/02 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F9/30 ,  G06F15/7832 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/30181

摘要： The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

摘要翻译： 本发明的数据处理器在写入寄存器的周期期间通过未使用的总线传送地址寄存器和程序寄存器的内容，并且在一个周期中执行需要地址计算的加载指令或存储指令，尽管处理器具有 两个总线和一个算术/逻辑单元。 此外，数据处理器通过将通用寄存器功能划分为四个地址寄存器和四个数据寄存器来分配寄存器之间的基本算术指令和加载/存储指令，其具有一个字节的基本指令字长度。

公开(公告)号：US5481679A

公开(公告)日：1996-01-02

申请号：US121799

申请日：1993-09-15

申请人： Nobuo Higaki ,  Toshimichi Matsuzaki

发明人： Nobuo Higaki ,  Toshimichi Matsuzaki

IPC分类号： G06F13/36 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4027 ,  G06F13/28 ,  G06F15/7817

摘要： A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed. Hence, data throughput on the buses can be improved and the load capacity can be reduced, which leads to heightening of the clock frequency.

摘要翻译： 描述了一种数据处理装置，包括连接指令存储单元和指令准备单元的第一总线，连接指令执行单元和数据存储单元的第二总线，总线选择性地电连接和断开第一和第二总线， 以及控制单元，其响应于指令准备单元和指令执行单元的操作来控制总线开关的操作。 当通过总线开关连接第一和第二总线时，可以执行从指令准备单元到数据存储单元的访问以及从指令执行单元到指令存储单元的访问。 另一方面，当总线未连接时，可以同时执行从指令准备单元的指令和来自指令执行单元的数据访问。 因此，可以提高总线上的数据吞吐量，并且可以减小负载能力，从而导致时钟频率的提高。

公开(公告)号：US5628018A

公开(公告)日：1997-05-06

申请号：US333747

申请日：1994-11-03

申请人： Toshimichi Matsuzaki ,  Nobuo Higaki

发明人： Toshimichi Matsuzaki ,  Nobuo Higaki

IPC分类号： G06F9/48 ,  G06F13/24 ,  G06F13/26

CPC分类号： G06F13/26

摘要： The object of the present invention is to provide an interruption processing apparatus which allows for improvements in operational speed and offers flexibility for a variety of systems, while using a lower amount of hardware. When an interruption occurs, then for the present invention shown in FIG. 2 , the corresponding interruption request flag in the interruption control register 1 in the group interruption control unit 5 is set. The interruption request unit 2 then outputs the interruption signal to the CPU 6 based on the interruption request flag. The interruption level arbitration unit 3 adjusts any conflict with other group control units and outputs, as the arbitration result, a signal showing whether output is possible or not for the interruption signal. The group number output unit 4 then outputs the fixed group number for the group in accordance with the arbitration result in response to access from the CPU 6. Once the CPU 6 receives the interruption request signal, no matter from what group interruption control unit the interruption was from, it activates the start of a program starting at the same address.

摘要翻译： 本发明的目的是提供一种中断处理装置，其允许提高操作速度并且在使用较少量的硬件的同时为各种系统提供灵活性。 当发生中断时，对于图1所示的本发明， 如图2所示，组中断控制单元5中的中断控制寄存器1中的相应中断请求标志被置位。 然后，中断请求单元2基于中断请求标志将中断信号输出到CPU6。 中断级别仲裁单元3调整与其他组控制单元的任何冲突，并且作为仲裁结果输出表示对于中断信号是否可以输出的信号。 组号输出单元4然后响应于来自CPU 6的访问，根据仲裁结果输出用于该组的固定组号。一旦CPU 6接收到中断请求信号，无论从什么组中断控制单元中断 来自，它激活从同一地址开始的程序的开始。

公开(公告)号：US08719827B2

公开(公告)日：2014-05-06

申请号：US13179614

申请日：2011-07-11

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F1/00

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US20100318707A1

公开(公告)日：2010-12-16

申请号：US12866061

申请日：2008-08-13

申请人： Tsuyoshi Tanaka ,  Nobuo Higaki ,  Takasi Inoue ,  Yosuke Kudo ,  Kazushi Kurata

发明人： Tsuyoshi Tanaka ,  Nobuo Higaki ,  Takasi Inoue ,  Yosuke Kudo ,  Kazushi Kurata

IPC分类号： G06F13/24 ,  G06F9/30

CPC分类号： G06F13/385 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683

摘要： An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status.

摘要翻译： 根据本发明的外部设备接入装置包括：地址控制单元，其从主机接收预取请求和预取数据读出请求，并执行预取操作和预取数据读出操作; 读出数据存储单元，存储通过预取操作读出的数据; 存储操作状态保持单元，其保存指示预取操作是否已经完成的预取操作状态; 以及接收信号生成单元，其向主设备输出表示预取数据读出请求已经从主机接受的接收信号。 基于预取操作状态，将指示预取操作的状态的第一信息输出到主机。

公开(公告)号：US07693514B2

公开(公告)日：2010-04-06

申请号：US10915535

申请日：2004-08-11

申请人： Yoshiaki Sakagami ,  Yoko Saito ,  Koji Kawabe ,  Takamichi Shimada ,  Nobuo Higaki

发明人： Yoshiaki Sakagami ,  Yoko Saito ,  Koji Kawabe ,  Takamichi Shimada ,  Nobuo Higaki

IPC分类号： H04Q7/20

CPC分类号： H04W4/02 ,  G05D1/0246 ,  G05D1/0274 ,  G05D2201/0207 ,  H04L67/12

摘要： In an event site or the like, a visitor may waste time and effort trying to find a spot where an event of interest may be taking place because the visitor is unable to look through the entire site from any particular spot. An information gathering robot roams in such an event site typically along a prescribed route, and notes spots of interest to transmit this information to a data server. The visitor can access the data server to find a spot of interest of his or her choice substantially on a real time basis.

摘要翻译： 在事件现场等中，访客可能会浪费时间和精力去尝试寻找可能发生的兴趣事件的地点，因为访问者无法从任何特定的地点查看整个站点。 信息收集机器人通常沿着规定的路线在这样的事件站点中漫游，并且记录将该信息发送到数据服务器的感兴趣点。 访问者可以访问数据服务器，实质上基于实时地查找他或她选择的兴趣点。

公开(公告)号：US20080267286A1

公开(公告)日：2008-10-30

申请号：US11572680

申请日：2005-02-23

申请人： Hideki Kuroki ,  Shigeki Fujii ,  Akihiko Ootani ,  Nobuo Higaki

发明人： Hideki Kuroki ,  Shigeki Fujii ,  Akihiko Ootani ,  Nobuo Higaki

IPC分类号： H04N7/12 ,  H04N7/32

CPC分类号： H04N19/00 ,  H04N19/11 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176

摘要： An image encoding device includes a prediction processing unit which performs prediction processing on m components among N components which constitute a quantized block; a first Coded Block Pattern (CBP) judging unit which judges whether or not (N−m) components include a non-zero component in a first operation mode, and whether or not (N−n) components include a non-zero component in a second operation mode; a second CBP judging unit which judges whether or not the m components on which the prediction processing has been performed include a non-zero component in the first operation mode, and whether or not n components include a non-zero component in the second operation mode; and a CBP generating unit which generates a CBP code indicating whether or not all the components of the block are 0 components based on the judgments made by the first and second judging units.

摘要翻译： 图像编码装置包括对构成量化块的N个成分中的m个成分进行预测处理的预测处理部; 第一编码块模式（CBP）判断单元，判定在第一操作模式中（Nm）分量是否包括非零分量，以及（Nn）分量是否包括第二操作模式中的非零分量 ; 第二CBP判断单元，判断在其中执行了预测处理的m个分量是否包括第一操作模式中的非零分量，以及n个分量是否包括第二操作模式中的非零分量 ; 以及CBP生成单元，其基于由所述第一判断单元和所述第二判断单元进行的判断，生成表示所述块的全部成分是否为0成分的CBP码。

公开(公告)号：US07386707B2

公开(公告)日：2008-06-10

申请号：US10338408

申请日：2003-01-08

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US07340100B2

公开(公告)日：2008-03-04

申请号：US10635778

申请日：2003-08-07

申请人： Nobuo Higaki ,  Yoshiaki Sakagami ,  Naoaki Sumida

发明人： Nobuo Higaki ,  Yoshiaki Sakagami ,  Naoaki Sumida

IPC分类号： G06K9/48

CPC分类号： G06F3/017 ,  G06K9/00335

摘要： A posture recognition apparatus recognizes instructions signified by postures of persons present in the surroundings, from images obtained with an image capture device. The posture recognition apparatus includes an outline extraction device that extracts an outline of a body which is a candidate for a person from the images; a distance calculation device that calculates a distance to the body being the candidate, from distance information of each pixel within the outline in the image; a search device that searches for a candidate for a hand of a person based on the outline and the distance to the body represented by the outline; and a posture determination device that determines an instruction corresponding to the relative position of the candidate for a hand and the outline, and outputs this determination result as a posture determination result.

摘要翻译： 姿势识别装置从通过图像拍摄装置获得的图像识别由周围的人存在的姿势所指示的指令。 姿势识别装置包括：轮廓提取装置，从图像中提取作为人的候选者的身体的轮廓; 距离计算装置，从图像中的轮廓内的每个像素的距离信息计算到作为候选者的身体的距离; 搜索装置，其基于轮廓和与轮廓所表示的身体的距离来搜索人的手的候选人; 以及姿势确定装置，其确定与手的候选者和轮廓的相对位置相对应的指令，并将该确定结果作为姿势确定结果输出。

公开(公告)号：US07305499B2

公开(公告)日：2007-12-04

申请号：US10901294

申请日：2004-07-29

申请人： Akihiro Furuta ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Tsuneyuki Suzuki

发明人： Akihiro Furuta ,  Nobuo Higaki ,  Tetsuya Tanaka ,  Tsuneyuki Suzuki

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F13/28

摘要： The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

摘要翻译： 本发明提供一种DMA传输控制器，包括：传输参数存储单元，用于存储总线占用时间值，并为多个逻辑处理器中的每一个传送一组或多组DMA传输的参数; 数据传送执行单元，用于基于DMA传输参数执行DMA传输; 控制单元，用于控制DMA传输参数的接收和发送以及DMA传输的开始和中断; 以及时间测量单元，用于当为每个逻辑处理器启动第一个DMA传输时开始测量总线占用时间。 当总线占用时间达到总线占用时间值时，控制单元基于与规定序列的逻辑处理器相关的传输参数中断当前执行的DMA传输以开始DMA传输。