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1.发明授权Pipeline data processor with arithmetic/logic unit capable of performing different kinds of calculations in a pipeline stage 失效具有算术/逻辑单元的管道数据处理器能够在流水线阶段执行不同类型的计算
公开(公告)号：US5649229A
公开(公告)日：1997-07-15
申请号：US419957
申请日：1995-04-10
CPC分类号： G06F9/30 , G06F15/7832 , G06F9/30043 , G06F9/30058 , G06F9/30181
摘要： The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.
摘要翻译： 本发明的数据处理器在写入寄存器的周期期间通过未使用的总线传送地址寄存器和程序寄存器的内容，并且在一个周期中执行需要地址计算的加载指令或存储指令，尽管处理器具有 两个总线和一个算术/逻辑单元。 此外，数据处理器通过将通用寄存器功能划分为四个地址寄存器和四个数据寄存器来分配寄存器之间的基本算术指令和加载/存储指令，其具有一个字节的基本指令字长度。
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公开(公告)号：US06253305B1
公开(公告)日：2001-06-26
申请号：US09226791
申请日：1999-01-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译： 提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。 从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。 存储单元存储存储在指令缓冲器中的指令的状态。 控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。
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公开(公告)号：US5966514A
公开(公告)日：1999-10-12
申请号：US643947
申请日：1996-05-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译： 提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。 从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。 存储单元存储存储在指令缓冲器中的指令的状态。 控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。
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公开(公告)号：US5440701A
公开(公告)日：1995-08-08
申请号：US932652
申请日：1992-08-20
CPC分类号： G06F9/30149 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3017 , G06F9/30181
摘要： Disclosed is a data processing apparatus comprising a decode device for decoding an instruction code including an operation code and two register designation codes and an instruction execution device for executing appropriate process according to the results decoded by the decode device, wherein the instruction execution device executes a first process when the two register designation codes are different from each other and executes a second process when they are equal.
摘要翻译： 公开了一种数据处理装置，包括用于对包括操作码和两个寄存器指定码的指令码进行解码的解码装置，以及用于根据解码装置解码的结果执行适当处理的指令执行装置，其中指令执行装置执行 当两个寄存器指定码彼此不同时执行第一处理，并且当它们相等时执行第二处理。
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公开(公告)号：US5418969A
公开(公告)日：1995-05-23
申请号：US278102
申请日：1994-07-20
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3287 , G06F9/3869 , Y02B60/1217 , Y02B60/1282
摘要： A microprocessor which reduces power consumption by monitoring the operating status of a plurality of operating units in the microprocessor to extract the unit which is recently most infrequently used to change the frequency of the operating clock supplied thereto in steps.
摘要翻译： 一种微处理器，其通过监视微处理器中的多个操作单元的操作状态来降低功耗，以提取最近最不常用的单元，以逐步改变提供给它的工作时钟的频率。
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6.发明授权Cache device for supplying a fixed word length of a variable instruction code and instruction fetch device 失效用于提供可变指令代码和指令获取装置的固定字长的缓存装置
公开(公告)号：US5301289A
公开(公告)日：1994-04-05
申请号：US80048
申请日：1993-06-21
CPC分类号： G06F9/3806 , G06F12/0875 , G06F9/3844
摘要： An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address. At the time of reading an instruction, first, a pair having an address of a branch instruction which address is the nearest to a head address of an instruction string to be read out is selected from a plurality of pairs, each pair including an address of a branch instruction which address is in a predetermined address range including the instruction string to be read out, or each pair of the plurality of pairs including a value obtained by subtracting a given value from the address of the branch instruction. Then, a branch destination address is selected and output from the pair which is selected first from the plurality of pairs.
摘要翻译： 指令提取设备包括高速缓存设备和分支历史表中的一个或两个。 高速缓存设备存储多对，每对包括分成最小单位指令和指令串地址的指令串。 在读取指令时，由至少两对的每个最小单位指令选择并输出指令串。 分支历史表存储多对，每对包括分支目的地地址和分支指令的地址集合，以及通过从地址中减去给定值而获得的值。 在读取指令时，首先从多个对中选择具有地址与要读出的指令串的头地址最接近的分支指令的地址的一对，每对包括 地址在包括要读出的指令串的预定地址范围内的分支指令，或包括通过从分支指令的地址中减去给定值而获得的值的每对对。 然后，从多个对中首先选择的一对中选择并输出分支目的地地址。
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公开(公告)号：US08716732B2
公开(公告)日：2014-05-06
申请号：US13137540
申请日：2011-08-24
申请人： Masao Kamiya , Masashi Deguchi
发明人： Masao Kamiya , Masashi Deguchi
IPC分类号： H01L33/00
CPC分类号： H01L33/42 , H01L33/20 , H01L33/382 , H01L33/46 , H01L33/60 , H01L2924/0002 , H01L2933/0025 , H01L2924/00
摘要： A light emitting element includes a semiconductor laminate structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, a part of the second semiconductor layer and the light emitting layer being removed to expose a part of the first semiconductor layer, a first reflecting layer on the semiconductor laminate structure and including an opening, the opening being formed in the exposed part of the first semiconductor layer, a transparent wiring electrode for carrier injection into the first semiconductor layer or the second semiconductor layer through the opening, a second reflecting layer formed on the transparent wiring electrode and covering a part of the opening so as to reflect light emitted from the light emitting layer and passing through the opening back to the first semiconductor layer.
摘要翻译： 发光元件包括半导体层叠结构，其包括第一导电类型的第一半导体层，发光层和不同于第一导电类型的第二导电类型的第二半导体层，第二半导体层的一部分和 去除所述发光层以暴露所述第一半导体层的一部分，所述半导体层叠结构上的第一反射层，并且包括开口，所述开口形成在所述第一半导体层的暴露部分中，用于载体的透明布线电极 通过所述开口注入到所述第一半导体层或所述第二半导体层中的第二反射层，形成在所述透明布线电极上并覆盖所述开口的一部分的第二反射层，以便反射从所述发光层发射的光并通过所述开口返回到 第一半导体层。
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公开(公告)号：US09117973B2
公开(公告)日：2015-08-25
申请号：US13317692
申请日：2011-10-26
申请人： Masashi Deguchi
发明人： Masashi Deguchi
摘要： A semiconductor light emitting element includes a semiconductor multilayer structure including a first conductive type layer, a second conductive type layer and a light emitting layer sandwiched between the first conductive type layer and the second conductive type layer, a first transparent electrode formed on the second conductive type layer, a reflecting layer formed on the first transparent electrode, and including a smaller area than the first transparent electrode, a second transparent electrode formed on the first transparent electrode so as to cover the reflecting layer, and a pad electrode formed on the second transparent electrode and in a region above the reflecting layer.
摘要翻译： 半导体发光元件包括半导体多层结构，其包括第一导电类型层，第二导电类型层和夹在第一导电类型层和第二导电类型层之间的发光层，形成在第二导电类型层上的第一透明电极 形成在第一透明电极上并具有比第一透明电极小的区域的反射层，形成在第一透明电极上以覆盖反射层的第二透明电极和形成在第二透明电极上的第二透明电极的焊盘电极 透明电极和反射层上方的区域。
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9.发明授权公开(公告)号：US09099627B2
公开(公告)日：2015-08-04
申请号：US13824286
申请日：2011-07-12
申请人： Shingo Totani , Masashi Deguchi , Miki Moriyama
发明人： Shingo Totani , Masashi Deguchi , Miki Moriyama
CPC分类号： H01L33/60 , H01L33/38 , H01L33/44 , H01L33/46 , H01L2933/0025
摘要： Sample A is produced by sequentially forming a first insulating film of SiO2 and a reflective film on a sapphire substrate. Sample B is produced by sequentially forming a first insulating film of SiO2, a reflective film, and a second insulating film of SiO2 on a sapphire substrate. In both samples A and B, the reflectance of the reflective film was measured at a wavelength of 450 nm before and after heat treatment. Heat treatment was performed at 600° C. for three minutes. As shown in FIG. 1, in Al/Ag/Al where Al has a thickness of 1 Å to 30 Å, Ag/Al where Al has a thickness of 20 Å, and Al/Ag/Al/Ag/Al where Al has a thickness of 20 Å, the reflectance was 95% or more, which is equivalent to or higher than that of Ag even after the heat treatment.
摘要翻译： 通过在蓝宝石衬底上依次形成SiO 2的第一绝缘膜和反射膜来制造样品A. 样品B通过在蓝宝石衬底上依次形成SiO 2的第一绝缘膜，反射膜和SiO 2的第二绝缘膜来制造。 在样品A和B中，在热处理前后在450nm的波长下测量反射膜的反射率。 在600℃下进行热处理3分钟。 如图所示。 如图1所示，在Al / Ag / Al中，其中Al具有厚度为的厚度为的Al / Ag / Al，Al的厚度为Al，Al / Ag / Al / Ag / Al，其中Al的厚度为 反射率为95％以上，即使在热处理后也等于或高于Ag。
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公开(公告)号：US09024342B2
公开(公告)日：2015-05-05
申请号：US13200927
申请日：2011-10-05
申请人： Masao Kamiya , Masashi Deguchi
发明人： Masao Kamiya , Masashi Deguchi
摘要： A semiconductor light emitting element includes a semiconductor multilayer structure including a first conductive type layer, a second conductive type layer, and a light emitting layer sandwiched between the first conductive type layer and the second conductive type layer, and a reflecting layer formed on the second conductive type layer for reflecting the light emitted from the light emitting layer. The light is extracted in a direction from the light emitting layer toward the first conductive type layer. The first conductive type layer includes a concavo-convex region on a surface thereof not opposite to the light emitting layer, for changing a path of light, and at least a part of the reflecting layer is formed extending to right above an edge of the concavo-convex region.
摘要翻译： 半导体发光元件包括半导体多层结构，其包括第一导电类型层，第二导电类型层和夹在第一导电类型层和第二导电类型层之间的发光层，以及反射层，形成在第二导电类型 导电型层，用于反射从发光层发射的光。 沿着从发光层朝向第一导电型层的方向提取光。 第一导电类型层包括在与发光层不相对的表面上的凹凸区域，用于改变光的路径，并且反射层的至少一部分形成为延伸到凹凸的边缘的正上方 -convex区域。
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