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    Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask
    1.
    发明申请
    Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask 失效
    用于形成掩模图案的方法和系统，制造半导体器件的方法，在数据上形成掩模图案的系统，单元库和形成光掩模的方法

    公开(公告)号：US20050064302A1

    公开(公告)日：2005-03-24

    申请号：US10933334

    申请日：2004-09-03

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shoichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shoichi Inoue

    IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01J37/302 ,  H01L21/027 ,  G03F9/00 ,  G21K5/10 ,  H01J37/08

    CPC分类号： G03F1/36 ,  H01J37/3026 ,  H01J2237/31769

    摘要： A method of forming a mask pattern comprises the following steps. A second cell library is prepared by making process proximity effect correction with respect to cell patterns stored in a first cell library. The second cell library stores corrected cell patterns. A first corrected cell pattern and a second corrected cell pattern of the corrected cell patterns are placed so that an edge of the first corrected cell pattern and an edge of the second corrected cell pattern contact or come close to or overlap each other. A boundary pattern at the boundary neighborhood between the first corrected cell pattern and the second corrected cell pattern is extracted. Process proximity effect correction is made with respect to the boundary pattern.

    摘要翻译： 形成掩模图案的方法包括以下步骤。 通过相对于存储在第一个细胞库中的细胞图案进行过程接近效应校正来制备第二个细胞库。 第二个细胞库存储校正的细胞图案。 放置经校正的单元图案的第一校正单元图案和第二校正单元图形，使得第一校正单元图案的边缘和第二校正单元图案的边缘彼此接近或重叠。 提取在第一校正单元图案和第二校正单元图案之间的边界邻域处的边界图案。 相对于边界图案进行过程接近效应校正。

    Method for making a design layout and mask
    3.
    再颁专利
    Method for making a design layout and mask 有权
    制作设计布局和面具的方法

    公开(公告)号：USRE42302E1

    公开(公告)日：2011-04-19

    申请号：US11905862

    申请日：2007-10-04

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

    摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。

    Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method
    4.
    发明申请
    Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 审中-公开
    半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法

    公开(公告)号：US20100275174A1

    公开(公告)日：2010-10-28

    申请号：US12801895

    申请日：2010-06-30

    申请人： Ayako Nakano ,  Satoshi Tanaka ,  Toshiya Kotani

    发明人： Ayako Nakano ,  Satoshi Tanaka ,  Toshiya Kotani

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

    摘要翻译： 从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。 基于第一设计数据计算半导体集成电路的第一特性。 通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。 基于第二设计数据计算半导体集成电路的第二特性。 检查第一特性和第二特性之间的特性差是否落在公差之内。 当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。

    Method of setting process parameter and method of setting process parameter and/or design rule
    7.
    发明授权
    Method of setting process parameter and method of setting process parameter and/or design rule 有权
    设置过程参数的方法和设置过程参数和/或设计规则的方法

    公开(公告)号：US07120882B2

    公开(公告)日：2006-10-10

    申请号：US11105431

    申请日：2005-04-14

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

    IPC分类号： G06F17/50

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

    摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

    Method of manufacturing a photo mask and method of manufacturing a semiconductor device
    8.
    发明授权
    Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权
    制造光掩模的方法和制造半导体器件的方法

    公开(公告)号：US07090949B2

    公开(公告)日：2006-08-15

    申请号：US10724738

    申请日：2003-12-02

    申请人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

    发明人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

    IPC分类号： G01F9/00

    CPC分类号： G03F1/36 ,  G03F1/68

    摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.

    摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。

    Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus
    10.
    发明授权
    Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus 失效
    掩模数据产生装置，用于产生掩模数据的计算机实现方法和用于控制掩模数据产生装置的计算机程序

    公开(公告)号：US06907596B2

    公开(公告)日：2005-06-14

    申请号：US10385624

    申请日：2003-03-12

    申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe

    发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe

    IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  H01L21/82 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.

    摘要翻译： 一种掩模数据生成装置，包括：分割模块，被配置为提取线段并将所提取的线段划分成合适的长度; 校正值计算模块，被配置为从每个分割边缘计算校正值计算点; 第一计算中心点计算模块，被配置为设置第一计算的中心点和图案的形状; 第一矩形区域准备模块，被配置为准备第一模拟区域和彼此重叠的多个第一矩形区域; 第二计算中心点计算模块，被配置为获取第二矩形区域，并且基于所述第二矩形区域计算第二计算的中心点; 配置成获取第二模拟区域的第二模拟区域准备模块; 被配置为计算校正值的过程模拟执行模块; 以及配置为准备校正图案的校正图案准备模块。