公开(公告)号：US07051270B2

公开(公告)日：2006-05-23

申请号：US10110670

申请日：2001-08-20

申请人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

发明人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

IPC分类号： H03M13/03 ,  H03M13/00

CPC分类号： H03M13/3905 ,  H03M13/258 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/2972 ,  H03M13/6337 ,  H03M13/6577 ,  H03M13/658

摘要： A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×Iλt and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

摘要翻译： 接收作为输入的概率信息的解码器。 该概率信息是通过将通过接收值y T 与预定系数AMP乘以获得的信道值除以第一加法系数C SUB来获得的，以用于调节 通过将先验概率信息APP＆lt; T＆gt;＆lt;＆gt;＆lt; T＆gt;获得的概率信息1 / C A xAPP＆lt; SUB>通过第二加法系数C A A A的倒数，用于将先验概率信息APP 的振幅调整到软输出解码电路。 可以是大规模集成电路的软输出解码电路生成日志软输出C 1和/或外部信息1 / C＆lt; 使用用于调节软输出解码电路内部的算术运算幅度的加法系数的XEXT。

公开(公告)号：US07010051B2

公开(公告)日：2006-03-07

申请号：US09816272

申请日：2001-03-23

申请人： Jun Murayama ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto ,  Takashi Yokokawa

发明人： Jun Murayama ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto ,  Takashi Yokokawa

IPC分类号： H04L5/12

CPC分类号： H03M13/29 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2972 ,  H03M13/3988

摘要： Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “⅔” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

摘要翻译： 根据串行级联调制方式的纠错编码和解码是以高码率进行的。 编码装置1包括用于进行卷积运算的三个卷积编码器10,30和50; 两个交织器20和40用于重新排列数据输入的顺序; 以及多值映射电路60，用于基于预定的调制系统执行单个点的映射。 编码装置1通过卷积编码器10进行码本为“2/3”的卷积运算，进行卷积编码器10的外部码的编码，并且通过卷积编码器50进行码率为“1”的卷积运算 ，并且多值调制映射电路60将映射应用于8PSK调制系统的发送符号，以将其作为单个码传输符号输出。

公开(公告)号：US06901548B2

公开(公告)日：2005-05-31

申请号：US09821008

申请日：2001-03-29

申请人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto ,  Takashi Yokokawa

发明人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi ,  Kouhei Yamamoto ,  Takashi Yokokawa

IPC分类号： G06F11/10 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45 ,  H04L1/00 ,  H04L27/00 ,  H04L27/18 ,  H03M13/00

CPC分类号： H03M13/256 ,  H03M13/258 ,  H03M13/2972 ,  H03M13/3988

摘要： To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

摘要翻译： 根据串行级联的编码调制系统，具有小电路规模和高性能，进行纠错编码和解码。 编码装置1被设计成使得交织器20交织比特的顺序，使得所有权重相对于包括从卷积编码器10提供的一系列3比特的数据由卷积编码器30编码; 卷积编码器30相对于从交织器20提供的3比特的数据，尽可能地使输入比特的汉明距离的总值为最小欧几里得距离; 并且多值调制映射电路40使卷积编码器30中的输入比特的汉明距离随着I / Q平面上的信号点之间的距离变小，从卷积编码器30提供的3比特数据映射。

公开(公告)号：US07180968B2

公开(公告)日：2007-02-20

申请号：US10111724

申请日：2001-08-31

申请人： Toshiyuki Miyauchi ,  Kouhei Yamamoto

发明人： Toshiyuki Miyauchi ,  Kouhei Yamamoto

IPC分类号： H03D1/00

CPC分类号： H03M13/2957 ,  H03M13/27 ,  H03M13/2903 ,  H03M13/6566

摘要： To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.

摘要翻译： 为了通过小规模，简单的结构化电路适当地表示代码的擦除位置，每个元件解码器中的软输出解码电路（90）包括接收值和先验概率信息选择电路（154），以选择 输入待解码的接收值TSR和外部信息或交织数据TEXT，以软输出解码为准。 基于从内部擦除信息生成电路（152）提供的内部擦除位置信息IERS，接收到的值和先验概率信息选择电路（154）用一个符号代替由于穿孔等而不存在编码输出的位置， 可能性为“0”。 也就是说，接收的值和先验概率信息选择电路（154）输出确定与没有编码输出的位置相对应的位为“0”或“1”的概率的信息。

公开(公告)号：US06525680B2

公开(公告)日：2003-02-25

申请号：US09876701

申请日：2001-06-07

申请人： Kouhei Yamamoto ,  Toshiyuki Miyauchi

发明人： Kouhei Yamamoto ,  Toshiyuki Miyauchi

IPC分类号： H03M700

CPC分类号： H03M13/3911 ,  H03M13/3922 ,  H03M13/3927

摘要： A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.

摘要翻译： 解码器具有减小的电路尺寸，其不会不利地影响电路的解码性能。 该解码器包括一个加法/比较/选择电路，其被添加以产生对数似然性，并适于计算相对于变量表示的一维函数的校正项，并将一个预定值加到校正项上，以便提供统一符号 用于识别用于计算对数似然度的对数似然性的积极性或消极性。

公开(公告)号：US08166363B2

公开(公告)日：2012-04-24

申请号：US12066641

申请日：2006-09-07

申请人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

发明人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/118 ,  H03M13/6577 ,  H04L1/0057

摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化 值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。

公开(公告)号：US08103945B2

公开(公告)日：2012-01-24

申请号：US11959551

申请日：2007-12-19

申请人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

发明人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

IPC分类号： G06F11/00

CPC分类号： H03M13/114 ,  H03M13/1111 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936 ,  H03M13/2948 ,  H03M13/3905 ,  H03M13/4146

摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

公开(公告)号：US08098775B2

公开(公告)日：2012-01-17

申请号：US12403445

申请日：2009-03-13

申请人： Takashi Yokokawa ,  Naoki Yoshimochi ,  Toshiyuki Miyauchi ,  Takashi Horiguti ,  Satoru Hori

发明人： Takashi Yokokawa ,  Naoki Yoshimochi ,  Toshiyuki Miyauchi ,  Takashi Horiguti ,  Satoru Hori

IPC分类号： H04L27/06

CPC分类号： H03M13/41

摘要： A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.

摘要翻译： 数据处理装置包括：分支度量计算部，被配置为计算分支度量; 配置为计算状态度量的状态度量计算部分; 检测部，被配置为检测最小状态度量; 存储部，被配置为将状态存储为存活状态; 以及选择部，被配置为选择候选。

公开(公告)号：US20090304111A1

公开(公告)日：2009-12-10

申请号：US12066641

申请日：2006-09-07

申请人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

发明人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

IPC分类号： H03K9/00

CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/118 ,  H03M13/6577 ,  H04L1/0057

摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果， 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。

公开(公告)号：US20060015791A1

公开(公告)日：2006-01-19

申请号：US10523452

申请日：2004-05-28

申请人： Atsushi Kikuchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kazuo Watanabe ,  Makiko Kan

发明人： Atsushi Kikuchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Kazuo Watanabe ,  Makiko Kan

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1836 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936

摘要： The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

摘要翻译： 本发明涉及适用于对通过使用环R上的线性码编码的编码数据进行解码的解码方法和解码器，程序，记录和再现装置和方法以及再现装置和方法。 低密度处理单元执行奇偶校验矩阵低密度处理，对获得的接收字中包含的奇偶校验矩阵的行进行线性组合，并根据线性组合结果生成奇偶校验矩阵，从而减少 在步骤S21中用于解码的奇偶校验矩阵的密度。然后，在步骤S22，LDPC解码单元通过使用通过使用密度减小的奇偶校验矩阵的和乘积算法（SPA）来执行解码 在步骤S2执行的处理。在步骤S22的处理完成的情况下，LDPC解码单元完成接收字的解码。 本发明可以用于纠错系统。