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公开(公告)号：US08103945B2
公开(公告)日：2012-01-24
申请号：US11959551
申请日：2007-12-19
IPC分类号： G06F11/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。
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公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。
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公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化 值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US08098775B2
公开(公告)日：2012-01-17
申请号：US12403445
申请日：2009-03-13
IPC分类号： H04L27/06
CPC分类号： H03M13/41
摘要： A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.
摘要翻译： 数据处理装置包括：分支度量计算部，被配置为计算分支度量; 配置为计算状态度量的状态度量计算部分; 检测部，被配置为检测最小状态度量; 存储部，被配置为将状态存储为存活状态; 以及选择部，被配置为选择候选。
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公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果， 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US07051270B2
公开(公告)日：2006-05-23
申请号：US10110670
申请日：2001-08-20
CPC分类号： H03M13/3905 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2957 , H03M13/2972 , H03M13/6337 , H03M13/6577 , H03M13/658
摘要： A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×Iλt and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.
摘要翻译： 接收作为输入的概率信息的解码器。 该概率信息是通过将通过接收值y
T 与预定系数AMP乘以获得的信道值除以第一加法系数C SUB来获得的，以用于调节 通过将先验概率信息APP＆lt; T＆gt;＆lt;＆gt;＆lt; T＆gt;获得的概率信息1 / C A xAPP＆lt; SUB>通过第二加法系数C A A A的倒数，用于将先验概率信息APP 的振幅调整到软输出解码电路。 可以是大规模集成电路的软输出解码电路生成日志软输出C 1和/或外部信息1 / C＆lt; 使用用于调节软输出解码电路内部的算术运算幅度的加法系数的XEXT。 -
公开(公告)号：US20100080330A1
公开(公告)日：2010-04-01
申请号：US12567856
申请日：2009-09-28
申请人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
发明人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
IPC分类号： H04B1/10
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。
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公开(公告)号：US20090235060A1
公开(公告)日：2009-09-17
申请号：US12403445
申请日：2009-03-13
IPC分类号： G06F9/38
CPC分类号： H03M13/41
摘要： A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.
摘要翻译： 数据处理装置包括：分支度量计算部，被配置为计算分支度量; 配置为计算状态度量的状态度量计算部分; 检测部，被配置为检测最小状态度量; 存储部，被配置为将状态存储为存活状态; 以及选择部，被配置为选择候选。
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公开(公告)号：US20090217121A1
公开(公告)日：2009-08-27
申请号：US11912481
申请日：2006-04-20
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译： 解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。 计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理，并且存储第一 在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理 并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。
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10.发明申请公开(公告)号：US20090190695A1
公开(公告)日：2009-07-30
申请号：US12361199
申请日：2009-01-28
申请人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
发明人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
IPC分类号： H03D3/00
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： Disclosed herein is a decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device including, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data, and decode second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data, and a synchronization detector configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data, the synchronization detector selecting and outputting one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
摘要翻译： 本文公开了一种解码装置，其对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码，并检测同步，该解码装置包括：解码器，被配置为对作为解调数据的第一解调数据进行解码， 正交调制信号，并且由同相轴数据和正交轴数据组成，并且对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码，以及同步检测器， 从通过对第一解调数据进行解码而获得的第一解码数据的预定信息符号序列之间的边界，并通过对第二解调数据进行解码获得的第二解码数据检测边界，同步检测器选择并输出第一解码数据和第二解码数据之一 基于de的结果 切割边界。
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