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公开(公告)号：US07155576B1
公开(公告)日：2006-12-26
申请号：US10446021
申请日：2003-05-27
CPC分类号： G06F12/0862
摘要： A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without the processor's intervention, to determine if the processor is lagging in processing the acquired packets. If so, data associated with unprocessed packets are pre-fetched from an external memory and placed in the cache memory without the processor's intervention. Moreover, packets destined for processing by the processor and placed into the cache memory are tracked, without the processor's intervention, to determine if the processor has, in fact, completed the processing of those packets. If so, data contained in the cache memory that is associated with the processed packets are invalidated, again without the processor's intervention.
摘要翻译： 一种用于管理耦合到中间节点处理器的高速缓冲存储器的技术。 在处理器干预的情况下，跟踪由中间节点获取的目的地由处理器处理的数据包，以确定处理器是否滞后于处理所获取的数据包。 如果是这样，与未处理的数据包相关联的数据将从外部存储器预取，并放置在高速缓冲存储器中，而无需处理器的干预。 而且，由处理器进行处理并被放置在高速缓冲存储器中的分组被跟踪，而无需处理器的介入，以确定处理器实际上是否完成了那些分组的处理。 如果是这样，与处理的数据包相关联的高速缓冲存储器中包含的数据无效，无需处理器的干预。
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公开(公告)号：US07302548B1
公开(公告)日：2007-11-27
申请号：US10174716
申请日：2002-06-18
CPC分类号： G06F15/167
摘要： A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.
摘要翻译： 提供了一种用于在多处理器环境中进行通信的方法，其包括在与待传送到目的地处理器的消息相关联的发起处理器处生成位。 该位位于与始发处理器相关联的发送寄存器中，并从发起处理器的发送寄存器转发到目标处理器的接收寄存器。 然后响应于该位被转置而产生中断信号。
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公开(公告)号：US07346059B1
公开(公告)日：2008-03-18
申请号：US10657497
申请日：2003-09-08
CPC分类号： H04L12/4625
摘要： A technique efficiently searches a hash table containing a plurality of “ranges.” In contrast with previous implementations, the technique performs fewer searches to locate one or more ranges stored in the hash table. To that end, the hash table is constructed so each hash-table entry is associated with a different linked list, and each linked-list entry stores, inter alia, “signature” information and at least one pair of values defining a range associated with the signature. The technique modifies the signature based on the results of one or more preliminary range checks. As a result, the signature's associated ranges are more evenly distributed among the hash table's linked lists. Thus, the linked lists are on average shorter in length, thereby enabling faster and more efficient range searches. According to an illustrative embodiment, the technique is applied to flow-based processing implemented in an intermediate network node, such as a router.
摘要翻译： 技术有效地搜索包含多个“范围”的散列表。 与先前的实现相比，该技术执行较少的搜索来定位存储在散列表中的一个或多个范围。 为此，构建哈希表，使得每个散列表条目与不同的链表相关联，并且每个链表列表条目尤其存储“签名”信息和至少一对定义与 签名。 该技术基于一个或多个初步范围检查的结果修改签名。 因此，签名的关联范围在哈希表的链表之间更均匀地分布。 因此，链表的长度平均更短，从而实现更快更有效的范围搜索。 根据说明性实施例，该技术被应用于在诸如路由器的中间网络节点中实现的基于流的处理。
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公开(公告)号：US07411957B2
公开(公告)日：2008-08-12
申请号：US10811195
申请日：2004-03-26
CPC分类号： H04L49/901 , H04L47/32 , H04L49/90 , H04L49/9042 , H04L49/9047 , H04L63/1416 , H04L63/1458
摘要： A system and method is provided for automatically identifying and removing malicious data packets, such as denial-of-service (DoS) packets, in an intermediate network node before the packets can be forwarded to a central processing unit (CPU) in the node. The CPU's processing bandwidth is therefore not consumed identifying and removing the malicious packets from the system memory. As such, processing of the malicious packets is essentially “off-loaded” from the CPU, thereby enabling the CPU to process non-malicious packets in a more efficient manner. Unlike prior implementations, the invention identifies malicious packets having complex encapsulations that can not be identified using traditional techniques, such as ternary content addressable memories (TCAM) or lookup tables.
摘要翻译： 提供了一种系统和方法，用于在分组可以转发到节点中的中央处理单元（CPU）之前自动识别和去除中间网络节点中的恶意数据分组，例如拒绝服务（DoS）分组。 因此，CPU的处理带宽不被识别并从系统内存中删除恶意数据包。 因此，恶意数据包的处理本质上从CPU中“卸载”，从而使CPU能够以更有效的方式处理非恶意数据包。 与先前的实现不同，本发明识别具有复杂封装的恶意数据包，这些封装不能使用诸如三进制内容可寻址存储器（TCAM）或查找表之类的传统技术来识别。
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公开(公告)号：US5011997A
公开(公告)日：1991-04-30
申请号：US105857
申请日：1987-10-07
申请人： James R. Hazen , William R. Lee
发明人： James R. Hazen , William R. Lee
IPC分类号： C07C211/52 , B01J23/40 , C07B61/00 , C07C67/00 , C07C209/00 , C07C209/42 , C07C209/50 , C07C209/56 , C07C209/58 , C07C211/50 , C07C211/58
CPC分类号： C07C209/56 , C07C209/58
摘要： This invention is an improved process for preparing 2,2-bis(4-aminophenyl)hexafluoropropane which comprises subjecting 2,2-bis(4-aminocarbonylphenyl)hexafluoropropane to the Hofmann reaction and then treating that reaction product under reducing conditions to produce the desired amine in high yield.
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公开(公告)号：USD356730S
公开(公告)日：1995-03-28
申请号：US13347
申请日：1993-09-23
申请人： William R. Lee
设计人： William R. Lee
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公开(公告)号：US07174394B1
公开(公告)日：2007-02-06
申请号：US10171957
申请日：2002-06-14
IPC分类号： G06F3/00
CPC分类号： G06F5/065 , G06F2205/064
摘要： The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.
摘要翻译： 本发明提供了一种用于多个独立处理器以在耦合到协处理器的上下文存储器中同时组合请求的系统和方法。 耦合到上下文存储器的写管理器组织从多个处理器接收的段以形成对协处理器的请求。 每个接收的段指示上下文存储器中的位置，例如索引的存储器块，其中应该存储段。 说明性地，写入管理器将接收到的段解析为上下文存储器的适当块，并且检测何时已经接收到请求的最后段。 可以根据预定的地址位来识别最后一个段，例如， 一个高位位，即被设置。 当写入管理器接收到请求的最后一个段时，写入管理器（1）完成在上下文存储器的一个块中组合该请求，（2）将与索引FIFO中的存储器块相关联的索引排入队列，以及（3） 设置与存储器块相关联的有效位。 通过设置有效位，写入管理器防止新接收的段覆盖尚未转发到协处理器的组合请求。 当索引到达索引FIFO的头部时，请求从上下文存储器的索引块中出发并转发到协处理器。
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8.发明授权System and method for decrementing a reference count in a multicast environment 有权在多播环境中递减引用计数的系统和方法公开(公告)号：US06895481B1
公开(公告)日：2005-05-17
申请号：US10189660
申请日：2002-07-03
CPC分类号： H04L12/1854
摘要： A method for decrementing a reference count in a multicast environment is provided that includes receiving an access request for a particle stored in a memory element. The memory unit is then accessed in response to the access request, the particle being read from the memory element. The particle includes a plurality of data segments, a selected one or more of which includes a first reference count associated with the particle. The particle is then presented to a target that generated the access request. The first reference count associated with the selected one or more data segments is then decremented in order to generate a second reference count. At least one of the plurality of data segments with the second reference count is then written to the memory element.
摘要翻译： 提供了一种用于递减多播环境中的引用计数的方法，包括接收对存储在存储器元件中的粒子的访问请求。 然后响应于访问请求访问存储器单元，从存储器元件读取该粒子。 粒子包括多个数据段，所选择的一个或多个数据段包括与该粒子相关联的第一参考计数。 然后将粒子呈现给生成访问请求的目标。 然后，与所选择的一个或多个数据段相关联的第一参考计数被递减，以便产生第二参考计数。 然后将具有第二参考计数的多个数据段中的至少一个写入存储器元件。
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公开(公告)号：US06477691B1
公开(公告)日：2002-11-05
申请号：US09542025
申请日：2000-04-03
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a “virtual design” and its automatic synthesis into a “real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.
摘要翻译： 在抽象层面描述片上系统的过程和安排。 考虑到创建一个“虚拟设计”及其自动综合成为一个包含图书馆IP块的实际设计以及它们之间所有必需的互连和接口逻辑。与系统相关的复杂性，时间和成本显着降低 因此，可以享受到芯片设计。
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公开(公告)号：US06050627A
公开(公告)日：2000-04-18
申请号：US30523
申请日：1998-02-24
申请人： William R. Lee
发明人： William R. Lee
IPC分类号： B60P3/40
CPC分类号： B60P3/40
摘要： A bed extender for extending the usable bed length of a vehicle. The extender includes hitch connecting apparatus, supporting apparatus, and positioning apparatus. The hitch connecting apparatus removably connects the bed extender with the orifice of a receiver hitch so as to allow the bed extender to be completely removed from the vehicle when the bed extender is not in use. The supporting apparatus supports a load when the load is substantially beyond the length of the bed of the vehicle so as to allow the weight of that portion of the load beyond the vehicle bed to be translated to the receiver hitch via the supporting apparatus and the hitch connecting apparatus. The positioning apparatus attaches the hitch connecting apparatus to the supporting apparatus and is substantially vertical. The positioning apparatus has an upper end connected to the supporting apparatus and a lower end connected to the hitch connecting apparatus and is of appropriate length so as to allow the supporting apparatus to be at least substantially the same height as the vehicle bed of the vehicle and is adjustable so as to allow the height of the supporting apparatus to be adjusted relative to the receiver hitch of the vehicle so as to accommodate various vehicle models and tailgate configurations.
摘要翻译： 一种用于延长车辆的可用床长的床用延伸器。 扩展器包括搭接连接装置，支撑装置和定位装置。 挂钩连接装置可以将床架延伸器与接收器搭接口的孔部可拆卸地连接，以便在不使用底座延伸器时允许床架延伸器完全从车辆上移除。 当负载基本上超过车辆床的长度时，支撑装置支撑负载，以便允许超过车床的负载部分的重量通过支撑装置和搭接平移到接收器钩 连接装置。 定位装置将挂钩连接装置连接到支撑装置并且基本垂直。 定位装置具有连接到支撑装置的上端和连接到搭接连接装置的下端，并且具有适当的长度，以便允许支撑装置与车辆的车床至少大致相同的高度， 是可调节的，以便允许支撑装置的高度相对于车辆的接收器搭扣进行调节，以适应各种车型和尾门结构。
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