公开(公告)号：US06444523B1

公开(公告)日：2002-09-03

申请号：US09860422

申请日：2001-05-18

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.

摘要翻译： 提供一种具有浮动栅极的存储器件的制造方法。 提供基板。 在衬底上执行沟道掺杂步骤，其中随后形成的存储器件的实际阈值电压变得大于预设阈值电压。 然后在衬底上顺序地形成堆叠栅极和源极/漏极区，以完成存储器件的形成。 通过实际阈值电压的增加来防止漏极导通泄漏。

公开(公告)号：US06649971B1

公开(公告)日：2003-11-18

申请号：US10064905

申请日：2002-08-28

申请人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： H01L29/7923

摘要： A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.

摘要翻译： 描述了用于降低第二位效应的NROM单元。 本发明的NORM单元由衬底，设置在衬底上的氧化硅/氮化硅/氧化硅（ONO）层，设置在氧化硅/氮化硅/氧化硅层上的栅极，源/漏区 配置在栅极旁边的衬底中，以及配置在源极/漏极区域和栅极旁边的ONO层之间的浅阱掺杂区域。 浅阱掺杂区域的深度足够小，以防止对流向源极/漏极区域的电流的干扰。

公开(公告)号：US06709921B2

公开(公告)日：2004-03-23

申请号：US09967717

申请日：2001-09-27

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

摘要翻译： 描述了具有分离浮动栅极的闪速存储器件的制造方法。 该方法提供了一种衬底，其中氧化物层和图案化的牺牲层依次形成在衬底上。 然后使用图案化的牺牲层作为掩模，进行离子注入，以在图案化牺牲层的侧面旁边的衬底中形成具有轻掺杂的源/漏区的源/漏区。 进一步进行各向同性蚀刻以去除图案化牺牲层的一部分，然后在图案化牺牲层的侧壁上形成两个导电间隔物。 然后去除由两个导电间隔物暴露的图案化牺牲层和氧化物层以形成两个浮动栅极。 随后，在基板上形成电介质层和控制栅极。

公开(公告)号：US06455376B1

公开(公告)日：2002-09-24

申请号：US09874455

申请日：2001-06-05

申请人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

摘要翻译： 公开了一种制造闪速存储器的方法。 该方法在衬底上开始堆叠栅极。 在其上已经形成有堆叠栅极的衬底上执行浅结掺杂，其中堆叠的栅极用作掩模，以便在与栅极的两侧相邻的衬底中形成浅结掺杂区域。 掩模层形成在衬底上以覆盖堆叠栅极的顶表面和侧壁，同时暴露浅结掺杂区域的部分。 在掩模层用作掩模的情况下，在衬底上进行深结掺杂以在衬底中邻近掩模层的两侧形成深结掺杂区域。 在去除掩模层之后，执行热处理以形成具有浅结掺杂区域和深掺杂区域的源极/漏极区域。

公开(公告)号：US06512696B1

公开(公告)日：2003-01-28

申请号：US09986932

申请日：2001-11-13

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/14

摘要： A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.

摘要翻译： 提供了一种编程和擦除SNNNS型非易失性存储单元的方法。 通过从漏极侧到中间氮化硅层的通道热电子注入来进行编程动作。 擦除操作通过从漏极侧到中间氮化硅层的通道热空穴注入来进行。 SNNNS型非易失性存储单元在低施加电压下提供高效率的热载流子注入，用于编程和擦除操作。 因此，本方法提供改进的性能特征，例如较短的编程/擦除时间和较低的施加电压。

公开(公告)号：US06790730B2

公开(公告)日：2004-09-14

申请号：US10156325

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/26586 ,  H01L27/112

摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

摘要翻译： 描述了一种用于掩模只读存储器件的制造方法。 该方法提供衬底，并且在衬底上形成掺杂导电层。 之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。 多个扩散区同时形成在基板中的棒状导电层的下方。 在电介质层上进一步形成图案化的导电层。

公开(公告)号：US06706575B2

公开(公告)日：2004-03-16

申请号：US10055265

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/115

摘要： A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有条带堆叠结构的基板。 然后在衬底旁边的衬底上形成掩埋漏极，并在掩埋漏极上形成绝缘层。 在衬底上顺序形成硅层和覆盖层。 然后，在垂直于埋地漏极的方向上连续地对盖层，硅层和条带堆叠结构进行图案化，其中条带层叠结构被图案化成多个栅极。 衬底氧化物层形成在栅极，衬底和硅层的暴露表面上。 此后，除去盖层，并在硅层的暴露表面上形成金属硅化物层。

公开(公告)号：US06665212B1

公开(公告)日：2003-12-16

申请号：US10065032

申请日：2002-09-12

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C16/30 ,  G11C2211/5634

摘要： The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.

摘要翻译： 多位闪存的参考电流产生电路。 将相同的升压字线电压施加到不同参考电流产生单元中的参考存储器单元的栅极端子，并且将不同的衬底电压施加到每个参考存储器单元的衬底，使得产生不同的参考电流。 这种布置降低了由于温度和源电压Vcc变化引起的参考电流的不同移位程度。

公开(公告)号：US06607957B1

公开(公告)日：2003-08-19

申请号：US10064614

申请日：2002-07-31

申请人： Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L218246

CPC分类号： H01L27/11568 ,  H01L21/28282

摘要： The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped polysilicon lines and expose a portion of the substrate. Afterwards, a thermal process is performed to form an oxide layer on the exposed substrate and sidewalls of the doped polysilicon lines. During the thermal process, the dopants are driven into the substrate to form a source/drain region, thus obtaining a plurality of bit lines including the doped polysilicon lines and the source/drain region. Following removal of the patterned mask layer, a self-aligned silicide layer is formed on the top surface of the bit lines. After removing the oxide layer, a silicon nitride stacked layer and a plurality of word lines are formed over the substrate.

摘要翻译： 本发明涉及一种用于制造氮化物只读存储器（NROM）的方法，包括：在衬底上形成掺杂多晶硅层，通过使用图案化掩模层来形成掺杂多晶硅层，以形成多个掺杂多晶硅线并暴露 衬底的一部分。 之后，进行热处理以在暴露的衬底和掺杂多晶硅线的侧壁上形成氧化物层。 在热处理期间，掺杂剂被驱动到衬底中以形成源极/漏极区域，从而获得包括掺杂多晶硅线路和源极/漏极区域的多个位线。 在去除图案化掩模层之后，在位线的顶表面上形成自对准的硅化物层。 在除去氧化物层之后，在衬底上形成氮化硅层叠层和多条字线。

公开(公告)号：US20070159893A1

公开(公告)日：2007-07-12

申请号：US11616770

申请日：2006-12-27

申请人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。