公开(公告)号：US06444523B1

公开(公告)日：2002-09-03

申请号：US09860422

申请日：2001-05-18

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.

摘要翻译： 提供一种具有浮动栅极的存储器件的制造方法。 提供基板。 在衬底上执行沟道掺杂步骤，其中随后形成的存储器件的实际阈值电压变得大于预设阈值电压。 然后在衬底上顺序地形成堆叠栅极和源极/漏极区，以完成存储器件的形成。 通过实际阈值电压的增加来防止漏极导通泄漏。

公开(公告)号：US06649971B1

公开(公告)日：2003-11-18

申请号：US10064905

申请日：2002-08-28

申请人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： H01L29/7923

摘要： A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.

摘要翻译： 描述了用于降低第二位效应的NROM单元。 本发明的NORM单元由衬底，设置在衬底上的氧化硅/氮化硅/氧化硅（ONO）层，设置在氧化硅/氮化硅/氧化硅层上的栅极，源/漏区 配置在栅极旁边的衬底中，以及配置在源极/漏极区域和栅极旁边的ONO层之间的浅阱掺杂区域。 浅阱掺杂区域的深度足够小，以防止对流向源极/漏极区域的电流的干扰。

公开(公告)号：US06709921B2

公开(公告)日：2004-03-23

申请号：US09967717

申请日：2001-09-27

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

摘要翻译： 描述了具有分离浮动栅极的闪速存储器件的制造方法。 该方法提供了一种衬底，其中氧化物层和图案化的牺牲层依次形成在衬底上。 然后使用图案化的牺牲层作为掩模，进行离子注入，以在图案化牺牲层的侧面旁边的衬底中形成具有轻掺杂的源/漏区的源/漏区。 进一步进行各向同性蚀刻以去除图案化牺牲层的一部分，然后在图案化牺牲层的侧壁上形成两个导电间隔物。 然后去除由两个导电间隔物暴露的图案化牺牲层和氧化物层以形成两个浮动栅极。 随后，在基板上形成电介质层和控制栅极。

公开(公告)号：US06455376B1

公开(公告)日：2002-09-24

申请号：US09874455

申请日：2001-06-05

申请人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

摘要翻译： 公开了一种制造闪速存储器的方法。 该方法在衬底上开始堆叠栅极。 在其上已经形成有堆叠栅极的衬底上执行浅结掺杂，其中堆叠的栅极用作掩模，以便在与栅极的两侧相邻的衬底中形成浅结掺杂区域。 掩模层形成在衬底上以覆盖堆叠栅极的顶表面和侧壁，同时暴露浅结掺杂区域的部分。 在掩模层用作掩模的情况下，在衬底上进行深结掺杂以在衬底中邻近掩模层的两侧形成深结掺杂区域。 在去除掩模层之后，执行热处理以形成具有浅结掺杂区域和深掺杂区域的源极/漏极区域。

公开(公告)号：US07031196B2

公开(公告)日：2006-04-18

申请号：US10757073

申请日：2004-01-14

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/00

CPC分类号： G11C16/0475 ,  G11C16/3468 ,  H01L21/28273 ,  H01L29/792 ,  H01L29/7923

摘要： A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

摘要翻译： 一种对存储器单元进行编程的方法包括将存储单元设置为第一栅极阈值电压的初始状态，执行处理顺序，包括：在栅极与第一结区域之间施加电压偏置，使电孔朝向 保持在捕获层中，并且评估响应于电压偏置产生的读取电流，以确定是否达到第二栅极阈值电压，其中第二栅极阈值电压低于第一栅极阈值电压。 通过改变栅极和第一结区域之间的电压偏压的一个或多个时间直到达到第二栅极阈值电压并且存储器单元处于编程状态来重复处理顺序多次。

公开(公告)号：US06914819B2

公开(公告)日：2005-07-05

申请号：US10653892

申请日：2003-09-04

申请人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

摘要翻译： 一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压 第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。

公开(公告)号：US06801453B2

公开(公告)日：2004-10-05

申请号：US10112871

申请日：2002-04-02

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.

摘要翻译： 一种用于非易失性存储单元的读取方案的方法。 非易失性存储单元包括衬底，源极，漏极以及由夹在第一绝缘层和第二绝缘层之间的非导电电荷捕获材料隔开的沟道之上的栅极。 该方法应用第一正的漏极 - 源极偏置，第二正的源极 - 衬底偏置和第三正向栅极 - 源偏置来读取在源极附近的捕获材料中的源极电荷。

公开(公告)号：US06657894B2

公开(公告)日：2003-12-02

申请号：US10112923

申请日：2002-03-29

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： A virtual ground nonvolatile memory cell array is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. Each of the nonvolatile memory cells is formed by an N channel MOSFET with a trapping layer formed between two isolating layers. In the erase state, the trapping layer stores an amount of electrons. A method for programming the virtual ground nonvolatile memory cell array is also disclosed. The potentials applied to the bitlines and wordlines in the array are preset to program nonvolatile memory cells and not to disturb cells adjacent to the nonvolatile memory cell to be programmed.

摘要翻译： 由布置成行和列的多个相邻的非易失性存储单元形成虚拟非易失性存储单元阵列，以形成阵列。 每个非易失性存储单元由具有在两个隔离层之间形成的捕获层的N沟道MOSFET形成。 在擦除状态下，捕获层存储一定量的电子。 还公开了一种用于编程虚拟接地非易失性存储单元阵列的方法。 应用于阵列中的位线和字线的电位被预设为非易失性存储器单元，而不是干扰与待编程的非易失性存储器单元相邻的单元。

公开(公告)号：US06822910B2

公开(公告)日：2004-11-23

申请号：US10248220

申请日：2002-12-29

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0466

摘要： A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.

摘要翻译： 描述了一种非易失性存储器件，其包括多个存储器单元，多个字线，多个漏极线和多个源极线，其中列中的两个相邻的存储器单元构成一个单元对，并且全部 单元对以行和列排列。 每个单元对中的两个存储单元共享源区，并且列中的两个相邻单元对共享漏区。 相同行中的存储单元的源极区域和栅极分别耦合到源极线和字线，并且同一列中的存储器单元的漏极区域耦合到漏极线。

公开(公告)号：US06646924B1

公开(公告)日：2003-11-11

申请号：US10064642

申请日：2002-08-02

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： H01L29/7885 ,  G11C16/0475 ,  H01L27/115

摘要： A non-volatile memory is described, which comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pair, and all of the cell pairs are arranged in rows and columns, wherein two cell pairs in the same row share a drain. The sources of the memory cells in the same row are connected to a source line, and the drains of the memory cells in the same row are connected to a drain line. The gates of the memory cells in the same column are coupled to a word line.

摘要翻译： 描述了一种非易失性存储器，其包括多个存储器单元，多个字线，多个漏极线和多个源极线。 同一行中的两个相邻的存储单元共享一个源并将其分组成一个单元对，并且所有的单元对排列成行和列，其中同一行中的两个单元对共享一个漏极。 同一行中的存储单元的源极连接到源极线，并且同一行中的存储器单元的漏极连接到漏极线。 同一列中的存储单元的栅极耦合到字线。