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1.发明授权
公开(公告)号：US5707744A
公开(公告)日：1998-01-13
申请号：US578810
申请日：1995-12-26
申请人： Tsu-Jae King , Jackson H. Ho
发明人： Tsu-Jae King , Jackson H. Ho
CPC分类号： H01L21/2022
摘要： A new polycrystalline silicon film which has been crystallized using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.
摘要翻译： 已经使用多晶硅锗（poly-Si1-xGex）覆盖膜结晶的新型多晶硅膜，以在基板的上表面“籽晶化”非晶硅膜。 多晶硅膜在多晶硅上表面附近的区域中不具有多晶硅和衬底上表面界面附近的区域中的成核位点和更多的晶界。 这表明结晶和晶体生长从多晶硅上表面发生并且朝向衬底上表面的方向进行。
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2.发明授权
公开(公告)号：US5893949A
公开(公告)日：1999-04-13
申请号：US578809
申请日：1995-12-26
申请人： Tsu-Jae King , Jackson H. Ho
发明人： Tsu-Jae King , Jackson H. Ho
CPC分类号： H01L21/2022
摘要： A new process to form a polycrystalline silicon film using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.
摘要翻译： 使用多晶硅 - 锗（poly-Si1-xGex）封盖膜在基板的上表面“籽晶化”非晶硅膜的方法来形成多晶硅膜的新工艺。 多晶硅膜在多晶硅上表面附近的区域中不具有多晶硅和衬底上表面界面附近的区域中的成核位点和更多的晶界。 这表明结晶和晶体生长从多晶硅上表面发生并且朝向衬底上表面的方向进行。
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公开(公告)号：US5693983A
公开(公告)日：1997-12-02
申请号：US235008
申请日：1994-04-28
IPC分类号： G02F1/136 , G02F1/1362 , H01L21/3205 , H01L23/52 , H01L23/532 , H01L29/786
CPC分类号： H01L23/53257 , G02F2001/136295 , H01L2924/0002 , H01L2924/3011
摘要： A conductive line in a thin-film structure such as an AMLCD array includes molybdenum and chromium so that it can be processed in a manner similar to chromium but has a greater conductivity than chromium due to the molybdenum. The conductive line can be produced by physical vapor deposition of a layer of a molybdenum-chromium (MoCr) alloy, which can then be masked and etched using photolithographic techniques in a manner similar to chromium. Proportions between 15 and 85 atomic percent of molybdenum can be processed more easily than pure molybdenum and are more conductive than pure chromium. Lines with between 40 and 60 atomic percent molybdenum can be used with a margin of error. To produce a tapered conductive line, sublayers of MoCr alloys with different etch rates can be produced and etched.
摘要翻译： 诸如AMLCD阵列的薄膜结构中的导线包括钼和铬，使得其可以以与铬类似的方式进行加工，但由于钼而具有比铬更高的导电性。 导电线可以通过钼 - 铬（MoCr）合金层的物理气相沉积来制造，然后可以以类似于铬的方式使用光刻技术进行掩模和蚀刻。 比例比纯钼更容易处理15到85原子％的钼的比例，比纯铬更加导电。 具有40至60原子％钼的线可以使用误差。 为了生产锥形导电线，可以生产和蚀刻具有不同蚀刻速率的MoCr合金的子层。
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公开(公告)号：US07863115B2
公开(公告)日：2011-01-04
申请号：US12331318
申请日：2008-12-09
申请人： Jackson H. Ho , Jeng Ping Lu
发明人： Jackson H. Ho , Jeng Ping Lu
CPC分类号： H01L27/124 , H01L21/268 , H01L29/41733 , H01L29/66765
摘要： An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.
摘要翻译： 实施例是制造平板显示器的方法和装置。 使用非晶硅或非晶硅兼容工艺形成用于显示面板的多晶硅结构。 多晶硅结构具有通道硅前体。 显示面板由使用多晶硅特定或多晶硅兼容工艺的多晶硅结构形成。
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公开(公告)号：US07129181B2
公开(公告)日：2006-10-31
申请号：US10943624
申请日：2004-09-17
IPC分类号： H01L21/302
CPC分类号： H01L21/76838 , B82Y30/00 , H01L21/28506 , H01L27/124
摘要： Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.
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公开(公告)号：US5528082A
公开(公告)日：1996-06-18
申请号：US235010
申请日：1994-04-28
IPC分类号： B05D7/00 , G02F1/1362 , H01L21/033 , H01L21/203 , H01L21/306 , H01L21/3213 , H01L23/48 , H01L23/52 , H01L27/01 , H01L29/76
CPC分类号： H01L21/0337 , H01L21/32139 , G02F1/136286 , Y10S257/92
摘要： A feature in a thin-film structure such as an AMLCD array has an edge with a tapered sidewall profile, reducing step coverage problems. The feature can be produced by producing a layer in which local etch rates vary in the thickness direction of the layer. The layer can then be etched to produce the feature with the tapered sidewall profile. The layer can be produced by physical vapor deposition. The layer can, for example, includes sublayers with different etch rates, either due to different atomic proportions of constituents or due to different etchants. Or local etch rates can vary continuously as a result of changing deposition conditions. Differences in etch rates or differences in etchant mixtures can be used to obtain a desired angle of elevation.
摘要翻译： 诸如AMLCD阵列之类的薄膜结构中的特征具有边缘具有锥形侧壁轮廓，从而减少了步骤覆盖问题。 该特征可以通过产生其中局部蚀刻速率在层的厚度方向上变化的层来产生。 然后可以蚀刻该层以产生具有锥形侧壁轮廓的特征。 该层可以通过物理气相沉积产生。 例如，该层可以包括具有不同蚀刻速率的子层，这是由于组分的原子比例不同或由于不同的蚀刻剂。 或者局部蚀刻速率可以随着沉积条件的改变而连续变化。 蚀刻速率的差异或蚀刻剂混合物的差异可用于获得期望的仰角。
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公开(公告)号：US08174078B2
公开(公告)日：2012-05-08
申请号：US12946762
申请日：2010-11-15
申请人： Jackson H. Ho , Jeng Ping Lu
发明人： Jackson H. Ho , Jeng Ping Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/124 , H01L21/268 , H01L29/41733 , H01L29/66765
摘要： An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.
摘要翻译： 实施例是制造平板显示器的方法和装置。 使用非晶硅或非晶硅兼容工艺形成用于显示面板的多晶硅结构。 多晶硅结构具有通道硅前体。 显示面板由使用多晶硅特定或多晶硅兼容工艺的多晶硅结构形成。
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公开(公告)号：US20110057193A1
公开(公告)日：2011-03-10
申请号：US12946762
申请日：2010-11-15
申请人： Jackson H. Ho , Jeng Ping Lu
发明人： Jackson H. Ho , Jeng Ping Lu
IPC分类号： H01L33/16 , H01L29/786
CPC分类号： H01L27/124 , H01L21/268 , H01L29/41733 , H01L29/66765
摘要： An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.
摘要翻译： 实施例是制造平板显示器的方法和装置。 使用非晶硅或非晶硅兼容工艺形成用于显示面板的多晶硅结构。 多晶硅结构具有通道硅前体。 显示面板由使用多晶硅特定或多晶硅兼容工艺的多晶硅结构形成。
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公开(公告)号：US20100237244A1
公开(公告)日：2010-09-23
申请号：US12408219
申请日：2009-03-20
申请人： Raj B. Apte , Jeng Ping Lu , Jackson H. Ho
发明人： Raj B. Apte , Jeng Ping Lu , Jackson H. Ho
IPC分类号： H01L31/00
CPC分类号： G09G3/006 , G01R31/308 , G09G3/3208 , G09G2360/147
摘要： A backplane test system is provided that uses a pressed or deposited resistive film and infra-red (IR) imaging to visualize and quantify the current drive of pixels. In one form, the system is used for measuring organic light-emitting-diode (OLED) backplanes or other current-actuated-display (CAD) backplanes.
摘要翻译： 提供了一种背板测试系统，其使用压制或沉积的电阻膜和红外（IR）成像来可视化和量化当前的像素驱动。 在一种形式中，该系统用于测量有机发光二极管（OLED）背板或其它电流驱动显示（CAD）背板。
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10.发明授权Organic thin-film transistor backplane with multi-layer contact structures and data lines 有权具有多层接触结构和数据线的有机薄膜晶体管背板公开(公告)号：US07566899B2
公开(公告)日：2009-07-28
申请号：US11316551
申请日：2005-12-21
IPC分类号： H01L51/10 , G02F1/1345
CPC分类号： H01L27/283 , H01L51/0037 , H01L51/0541 , H01L51/0545 , H01L51/105
摘要： A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.
摘要翻译： 背板电路包括有机薄膜晶体管（OTFT）的阵列，每个OTFT包括源极接触，漏极接触以及在源极和漏极接触之间延伸的有机半导体区域。 每行的漏极触点连接到地址线。 源极和漏极触点和地址线使用包括由相对便宜的金属（例如，铝或铜）形成的相对厚的基部的多层结构以及由高功函数形成的相对较薄的接触层制造， 与有机半导体呈现良好的电接触的低氧化金属（例如，金）形成在与基底的至少一个外表面相对的位置，并且至少部分地位于有机半导体与下面的介电层接触的界面区域中。
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