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公开(公告)号：US20250087559A1
公开(公告)日：2025-03-13
申请号：US18381630
申请日：2023-10-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , I-Fan Chang , Jia-Rong Wu
IPC: H01L23/48 , H01L21/768 , H01L23/532 , H01L23/58
Abstract: A TSV structure includes a substrate. A through via penetrates the substrate. A copper layer fills the through via. A trench is embedded in the substrate and surrounds the copper layer, and a material layer fills the trench. The material layer includes W, Cr, Ir, Re, Zr, SiOC glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass.
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公开(公告)号：US20230247914A1
公开(公告)日：2023-08-03
申请号：US18132989
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.
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公开(公告)号：US20210151664A1
公开(公告)日：2021-05-20
申请号：US16702576
申请日：2019-12-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , Ya-Huei Tsai , I-Fan Chang , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
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公开(公告)号：US20190043725A1
公开(公告)日：2019-02-07
申请号：US15688852
申请日：2017-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , Jie-Ning Yang , Chi-Ju Lee , Chun-Ting Chiang , Bo-Yu Su , Chih-Wei Lin , Dien-Yang Lu
IPC: H01L21/28 , H01L29/66 , H01L29/423
CPC classification number: H01L21/28167 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656
Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
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公开(公告)号：US12150313B2
公开(公告)日：2024-11-19
申请号：US18500994
申请日：2023-11-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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Patent Agency Ranking
公开(公告)号：US12052933B2
公开(公告)日：2024-07-30
申请号：US18132992
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.
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公开(公告)号：US11849592B2
公开(公告)日：2023-12-19
申请号：US17888451
申请日：2022-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
CPC classification number: H10B61/00 , G11C11/161 , H01F10/3254 , H01F41/34 , H01L23/528 , H01L23/5226 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US20230157182A1
公开(公告)日：2023-05-18
申请号：US18098091
申请日：2023-01-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , Ya-Huei Tsai , I-Fan Chang , Yu-Ping Wang
CPC classification number: H10N50/80 , H01F10/3254 , H01F41/34 , H10B61/00 , H10N50/01 , G11C11/161
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
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公开(公告)号：US11456331B2
公开(公告)日：2022-09-27
申请号：US16857152
申请日：2020-04-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L43/02 , H01L27/22 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H01L43/12 , H01L43/10
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.
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公开(公告)号：US20190006484A1
公开(公告)日：2019-01-03
申请号：US16043120
申请日：2018-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang , Chun-Ting Chiang , Chih-Wei Lin , Bo-Yu Su , Chi-Ju Lee
IPC: H01L29/51 , H01L29/49 , H01L21/3213 , H01L29/06 , H01L29/423 , H01L21/28 , H01L29/08 , H01L29/66 , H01L29/78
CPC classification number: H01L29/515 , H01L21/28088 , H01L21/28247 , H01L21/32139 , H01L21/7682 , H01L21/76897 , H01L29/0649 , H01L29/0847 , H01L29/42368 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66568 , H01L29/66795 , H01L29/7851
Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
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