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1.发明授权Method for forming semiconductor structure having through silicon via for signal and shielding structure 有权用于形成通过硅通孔用于信号和屏蔽结构的半导体结构的方法公开(公告)号：US08916471B1
公开(公告)日：2014-12-23
申请号：US13975382
申请日：2013-08-26
发明人： Ching-Li Yang , Chien-Li Kuo , Chung-Sung Chiang , Yu-Han Tsai , Chun-Wei Kang
IPC分类号： H01L21/44 , H01L29/40 , H01L21/768 , H01L23/552 , H01L23/538
CPC分类号： H01L21/76898 , H01L21/76897 , H01L23/481 , H01L23/5225 , H01L23/5384 , H01L24/16 , H01L2224/0401 , H01L2224/04042 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2924/3025
摘要： A method for forming a through silicon via for signal and a shielding structure is provided. A substrate is provided and a region is defined on the substrate. A radio frequency (RF) circuit is formed in the region on the substrate. A through silicon trench (TST) and a through silicon via (TSV) are formed simultaneously, wherein the TST encompasses the region to serve as a shielding structure for the RF circuit. A metal interconnection system is formed on the substrate, wherein the metal interconnection system comprises a connection unit that electrically connects the TSV to the RF circuit to provide a voltage signal.
摘要翻译： 提供一种用于形成用于信号的通硅通孔和屏蔽结构的方法。 提供衬底并且在衬底上限定区域。 在基板上的区域中形成射频（RF）电路。 同时形成贯通硅沟槽（TST）和贯穿硅通孔（TSV），其中TST包围用作RF电路的屏蔽结构的区域。 在基板上形成金属互连系统，其中金属互连系统包括将TSV电连接到RF电路以提供电压信号的连接单元。
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公开(公告)号：US11935854B2
公开(公告)日：2024-03-19
申请号：US18119266
申请日：2023-03-08
发明人： Chung-Sung Chiang , Chia-Wei Liu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC分类号： H01L23/00 , H01L23/488 , H01L23/532 , H01L25/065
CPC分类号： H01L24/06 , H01L23/488 , H01L23/53228 , H01L25/0655
摘要： A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.
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公开(公告)号：US20230008792A1
公开(公告)日：2023-01-12
申请号：US17406091
申请日：2021-08-19
发明人： Chung-Sung Chiang , Chia-Wei Liu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC分类号： H01L23/00 , H01L25/065 , H01L23/488 , H01L23/532
摘要： A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.
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公开(公告)号：US20150332996A1
公开(公告)日：2015-11-19
申请号：US14280680
申请日：2014-05-19
发明人： Chien-Li Kuo , Kuei-Sheng Wu , Ming-Tse Lin , Chung-Sung Chiang
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , G03F7/20
CPC分类号： H01L21/486 , G03F7/203 , G03F7/38 , G03F7/70 , H01L21/48 , H01L21/4846 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/065 , H01L2224/16145 , H01L2224/16227 , H01L2224/1701 , H05K3/0082 , H05K2201/10378
摘要： The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.
摘要翻译： 本发明提供一种包括多个电路设计和设置在电路设计上的最上层电路设计的插入器。 最大曝光区域被定义为可以通过光刻扫描器的单次射击来定义的最大尺寸。 电路设计的最小电路设计尺寸小于最大曝光区域的尺寸。 因此，电路设计分别仅由光刻扫描器的单个镜头形成。 最上面的电路设计的长度大于最大曝光区域的长度，因此电路设计是通过光刻地拼接两个光掩模形成的。
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5.发明公开公开(公告)号：US20240170423A1
公开(公告)日：2024-05-23
申请号：US18430670
申请日：2024-02-02
发明人： Chung-Sung Chiang , Chia-Wei Liu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC分类号： H01L23/00 , H01L23/488 , H01L23/532 , H01L25/065
CPC分类号： H01L24/06 , H01L23/488 , H01L23/53228 , H01L25/0655
摘要： A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.
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公开(公告)号：US20230223366A1
公开(公告)日：2023-07-13
申请号：US18119266
申请日：2023-03-08
发明人： Chung-Sung Chiang , Chia-Wei Liu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC分类号： H01L23/00 , H01L23/532 , H01L25/065 , H01L23/488
CPC分类号： H01L24/06 , H01L23/53228 , H01L25/0655 , H01L23/488
摘要： A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.
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公开(公告)号：US11640949B2
公开(公告)日：2023-05-02
申请号：US17406091
申请日：2021-08-19
发明人： Chung-Sung Chiang , Chia-Wei Liu , Yu-Ruei Chen , Yu-Hsiang Lin
IPC分类号： H01L23/48 , H01L23/00 , H01L23/532 , H01L23/488 , H01L25/065
摘要： A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.
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