公开(公告)号：US09947640B2

公开(公告)日：2018-04-17

申请号：US14287065

申请日：2014-05-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/16268 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/207 ,  H01L2924/00012

摘要： The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

公开(公告)号：US09929081B2

公开(公告)日：2018-03-27

申请号：US15256749

申请日：2016-09-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo

IPC分类号： H01L23/498 ,  H01L21/48 ,  C25D5/02 ,  C25D5/48 ,  C25D5/34 ,  H01L23/00 ,  C25D5/56 ,  C25D7/12 ,  H05K1/11 ,  H05K3/02 ,  H05K3/40 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/49822 ,  C25D5/02 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D5/56 ,  C25D7/12 ,  C25D7/123 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/80895 ,  H05K1/11 ,  H05K3/02 ,  H05K3/4007

摘要： An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.

公开(公告)号：US20160133518A1

公开(公告)日：2016-05-12

申请号：US14997594

申请日：2016-01-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo ,  Yung-Chang Lin

IPC分类号： H01L21/768 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L21/76898 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

摘要翻译： 半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。 此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。 在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

公开(公告)号：US09287173B2

公开(公告)日：2016-03-15

申请号：US13900565

申请日：2013-05-23

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

摘要翻译： 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US20160020175A1

公开(公告)日：2016-01-21

申请号：US14479526

申请日：2014-09-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo

IPC分类号： H01L23/538 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

公开(公告)号：US20150332996A1

公开(公告)日：2015-11-19

申请号：US14280680

申请日：2014-05-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo ,  Kuei-Sheng Wu ,  Ming-Tse Lin ,  Chung-Sung Chiang

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  G03F7/20

CPC分类号： H01L21/486 ,  G03F7/203 ,  G03F7/38 ,  G03F7/70 ,  H01L21/48 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1701 ,  H05K3/0082 ,  H05K2201/10378

摘要： The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.

摘要翻译： 本发明提供一种包括多个电路设计和设置在电路设计上的最上层电路设计的插入器。 最大曝光区域被定义为可以通过光刻扫描器的单次射击来定义的最大尺寸。 电路设计的最小电路设计尺寸小于最大曝光区域的尺寸。 因此，电路设计分别仅由光刻扫描器的单个镜头形成。 最上面的电路设计的长度大于最大曝光区域的长度，因此电路设计是通过光刻地拼接两个光掩模形成的。

公开(公告)号：US20150014828A1

公开(公告)日：2015-01-15

申请号：US13939184

申请日：2013-07-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chia-Fang Lin

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L23/481 ,  H01L23/535 ,  H01L23/585 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

摘要翻译： 本发明提供一种具有屏蔽结构的半导体器件。 半导体器件包括衬底，RF电路，屏蔽结构和互连系统。 基板包括有源侧和背面。 RF电路设置在基板的有源侧。 屏蔽结构设置在有源侧并且包围RF电路。 屏蔽结构接地。 屏蔽结构包括不穿透基板的屏蔽TST。 互连系统设置在基板的有源侧。 互连系统包括将信号电连接到RF电路的连接单元。

公开(公告)号：US20140291801A1

公开(公告)日：2014-10-02

申请号：US13854142

申请日：2013-04-01

申请人： United Microelectronics CORP.

发明人： Chu-Fu Lin ,  Chien-Li Kuo ,  Ching-Li Yang

IPC分类号： H01L23/525 ,  H01L23/00

CPC分类号： H01L23/5252 ,  H01L23/525 ,  H01L23/5254 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.

摘要翻译： 反熔丝编程方法包括以下步骤。 首先，提供绝缘层。 在绝缘层上限定反熔丝区域。 反熔丝嵌入在绝缘层的反熔丝区域内。 反熔丝包括至少第一导体和第二导体。 然后，通过激光去除绝缘层的一部分，以在绝缘层中形成抗熔丝开口。 第一导体的一部分和第二导体的一部分通过反熔丝开口露出。 之后，在反熔丝开口中形成凸起下的金属层，以电连接第一导体和第二导体。

公开(公告)号：US10199273B2

公开(公告)日：2019-02-05

申请号：US14997594

申请日：2016-01-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo ,  Yung-Chang Lin

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/06

摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

公开(公告)号：US09704841B2

公开(公告)日：2017-07-11

申请号：US14226802

申请日：2014-03-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Li Kuo

IPC分类号： H01L21/70 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.