公开(公告)号：US09312121B1

公开(公告)日：2016-04-12

申请号：US14511092

申请日：2014-10-09

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yi-Hui Lee ,  Tsung-Hung Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia-Chang Hsu ,  Shu-Min Huang ,  Hsin-Fu Huang

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855

Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.

Abstract translation: 提供了用于清洁接触孔并形成接触插塞的方法。 该方法包括以下步骤：提供硅衬底; 在硅衬底中形成接触孔; 执行预清洁处理以清洁接触孔; 并在接触孔中形成接触塞。 预清洗工艺包括以下步骤：进行氧化干蚀刻工艺; 执行温度等于或大于300℃的第一热退火工艺; 以等于或大于300℃的温度进行脱气处理; 并进行Ar等离子体蚀刻处理。

公开(公告)号：US09634125B2

公开(公告)日：2017-04-25

申请号：US15046467

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Wen-Jiun Shen ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/785

Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

公开(公告)号：US09698047B2

公开(公告)日：2017-07-04

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L29/78 ,  H01L27/11 ,  H01L21/768 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US20160372476A1

公开(公告)日：2016-12-22

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L21/768 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Abstract translation: 提供半导体器件和制造这种半导体器件的方法用于改进的FinFET存储器单元，以避免经常在位单元的金属触点之间发生电短路，其中餐触点位于相邻虚拟边缘单元的虚拟栅极旁边。 在一个实施例中，在衬底表面上的栅极层的图案化期间，使用改进的栅极槽图案来延伸与位线相邻的一个或多个栅极槽的长度，以便图形化和分割靠近金属的伪栅极线 活动存储单元的触点。 在另一个实施例中，在栅极线图案化期间，调整邻近有源存储器单元设置的一个或多个虚拟栅极线之间的距离，使得它们在虚设边缘单元内的位置移位以远离有源存储器的金属触点 细胞。

公开(公告)号：US09385191B2

公开(公告)日：2016-07-05

申请号：US14549523

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Wen-Jiun Shen ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7856

Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

Abstract translation: 提供FINFET结构。 FINFET结构包括衬底，PMOS元件，NMOS元件，STI结构和凸块结构。 基板包括与第一区域相邻的第一区域和第二区域。 PMOS元件设置在衬底的第一区域中，并且包括至少一个第一鳍结构。 NMOS元件设置在衬底的第二区域中并且包括至少一个第二鳍结构。 STI结构设置在第一翅片结构和第二翅片结构之间。 凸块结构设置在STI结构上并具有含碳介电材料。