-
公开(公告)号:US12024201B2
公开(公告)日:2024-07-02
申请号:US17392376
申请日:2021-08-03
Inventor: Prabuddha Chakraborty , Reiner Dizon , Christopher Vega , Joel B. Harley , Sandip Ray , Swarup Bhunia , Patanjali Sristi Lakshmiprasanna Sriramakumara
CPC classification number: B60W60/0025 , G05D1/101
Abstract: Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.
-
公开(公告)号:US11549897B2
公开(公告)日:2023-01-10
申请号:US17389601
申请日:2021-07-30
Inventor: Swarup Bhunia , Naren Vikram Raj Masna , Soumyajit Mandal , David Joseph Ariando
Abstract: An exemplary integrated nuclear quadrupole resonance-based detection system comprises a front-end device having a hand-held form factor, wherein the front-end device is configured to scan a sample in or near a sample coil using inbuild electronics and acquire a nuclear quadrupole resonance measurement. The system further includes a swappable sample coil that is attached to an opening at a face of the front-end device and is tuned to a resonant frequency of the sample; and a swappable impedance matching network that is attached to the opening at the face of the front-end device and is configured to tune the resonant frequency of the sample coil. The inbuild electronics comprises a wireless transfer module that is configured to communicate the acquired nuclear quadrupole resonance measurement with a back-end device of the integrated nuclear quadrupole resonance-based detection system. Other systems and methods are also provided.
-
公开(公告)号:US20210319101A1
公开(公告)日:2021-10-14
申请号:US17224559
申请日:2021-04-07
Inventor: Swarup Bhunia , Tamzidul Hoque , Abhishek Anil Nair , Patanjali Sristi Lakshmiprasanna Sriramakumara
IPC: G06F21/56
Abstract: The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.
-
公开(公告)号:US10586135B2
公开(公告)日:2020-03-10
申请号:US16011509
申请日:2018-06-18
Inventor: Roozbeh Tabrizian , Swarup Bhunia
IPC: G06K19/06 , G06K19/04 , G06K1/12 , H01L41/314 , H01L41/187 , H01L41/09 , G06K19/067
Abstract: Data is encoded for identification and labeling using a multitude of nano-electro-mechanical structures formed on a substrate. The number of such structures, their shapes, choice of materials, the spacing therebetween and the overall distribution of the structures result in a vibrational pattern or an acoustic signature that uniquely corresponds to the encoded data. A first group of the structures is formed in conformity with the design rules of a fabrication process used to manufacture the device that includes the structures. A second group of the structures is formed so as not to conform to the design rules and thereby to undergo variability as a result of the statistical variations that is inherent in the fabrication process.
-
公开(公告)号:US11480614B2
公开(公告)日:2022-10-25
申请号:US17097446
申请日:2020-11-13
Inventor: Swarup Bhunia , Shubhra Deb Paul
IPC: G01R31/3185 , G01R31/317 , G01R31/302 , G01R31/3181 , G01R31/3183 , G06F21/70 , G06F21/73 , H04L9/32 , G09C1/00
Abstract: The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.
-
6.
公开(公告)号:US20200380868A1
公开(公告)日:2020-12-03
申请号:US16885642
申请日:2020-05-28
Inventor: Swarup Bhunia , Prabuddha Chakraborty , Lili Du , Sandip Ray
Abstract: Various examples are provided related to multi-purpose context-aware bumps (CABs) that can support dynamic adaptation of form factors and functionality. In one example, a CAB system can include sensors distributed in a traffic network and communicatively coupled to a remotely located computing environment; context-aware bumps (CABs) placed in the traffic network and communicatively coupled to the remotely located computing environment; and a CAB application configured to adjust a form factor of a CAB in response to information obtained from the sensors and/or CABs. In another example, a method can include receiving, by a remotely located computing environment, traffic information from sensors distributed in a traffic network or CABs placed in the traffic network; communicating, by the remotely located computing environment, a form factor control to a CAB in response to the traffic information; and adjusting a form factor of the CAB in response to the form factor control.
-
公开(公告)号:US20190072506A1
公开(公告)日:2019-03-07
申请号:US16121439
申请日:2018-09-04
Inventor: Soumyajit Mandal , Swarup Bhunia , Naren Vikram Raj Masna , Cheng Chen , Mason Greer , Fengchao Zhang
IPC: G01N24/08 , G01R33/44 , G01R33/46 , G01N21/359
Abstract: An example includes performing near infra-red (NIR) spectrometry to provide NIR measurement data for a sample compound. The method also includes performing magnetic resonance (MR) spectrometry to provide MR measurement data for the sample compound. The method also includes analyzing, by a computing device, the MR measurement data in view of the NIR measurement data to characterize the sample compound.
-
公开(公告)号:US12210663B2
公开(公告)日:2025-01-28
申请号:US17573053
申请日:2022-01-11
Inventor: Swarup Bhunia , Md Moshiur Rahman , Aritra Dasgupta , Abdulrahman Alaql
Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods of protecting an integrated circuit. One such method comprises operating the integrated circuit under a normal mode of operation; detecting, by a decommission controller, a triggering condition for a decommission operation to be initiated for the integrated circuit; initiating, by the decommission controller, a decommission mode for the integrated circuit after detection of the triggering condition; and causing, by the decommission controller, functionality of the integrated circuit to be irreversibly disabled after initiating the decommission mode. Other methods, systems, and apparatus are also presented.
-
公开(公告)号:US11720654B2
公开(公告)日:2023-08-08
申请号:US17549184
申请日:2021-12-13
Inventor: Swarup Bhunia , Abdulrahman Alaql , Aritra Dasgupta , Md Moshiur Rahman
CPC classification number: G06F21/123 , G06F21/14 , G06F21/72 , G06F21/75
Abstract: The present disclosure provides systems and methods for timed unlocking and locking of hardware intellectual properties obfuscation. One such method includes determining whether received key inputs match a functional key sequence of an integrated circuit or a test key sequence of the integrated circuit; permanently enabling operation of the integrated circuit responsive to the received key inputs being determined to be a functional key sequence for permanently enabling operation of the integrated circuit; temporarily enabling operation of the integrated circuit responsive to the received key inputs being determined to be the test key sequence for temporarily enabling operation of the integrated circuit to perform testing of the functionality and disable thereafter; and locking sequential logic and combinational logic of the integrated circuit if the received key inputs are determined to not be either the functional key sequence or the test key sequence. Other systems and methods are also provided.
-
10.
公开(公告)号:US11657127B2
公开(公告)日:2023-05-23
申请号:US17120778
申请日:2020-12-14
Inventor: Swarup Bhunia , Md Moshiur Rahman , Abdulrahman Alaql
IPC: G06F21/14 , G06F9/448 , G06F30/327 , G06F21/60 , G06F21/75
CPC classification number: G06F21/14 , G06F9/4498 , G06F21/602 , G06F21/75 , G06F30/327
Abstract: The present disclosure describes exemplary methods and systems of protecting an integrated circuit. One exemplary method comprises receiving a plurality of key inputs for enabling operation of the integrated circuit; determining whether the received key inputs are correct key inputs for enabling operation of the integrated circuit; and if the received key inputs are determined to be incorrect key inputs, locking sequential logic and combinational logic of the integrated circuit until correct key inputs are received.
-
-
-
-
-
-
-
-
-