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公开(公告)号：US10340332B2
公开(公告)日：2019-07-02
申请号：US15774286
申请日：2016-09-17
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
Inventor： Min Ren , Yumeng Zhang , Cong Di , Jingzhi Xiong , Zehong Li , Jinping Zhang , Wei Gao , Bo Zhang
Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.
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公开(公告)号：US09741837B2
公开(公告)日：2017-08-22
申请号：US15209745
申请日：2016-07-13
Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA , INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Inventor： Jinping Zhang , Yadong Shan , Gaochao Xu , Xin Yao , Jingxiu Liu , Zehong Li , Min Ren , Bo Zhang
IPC: H01L29/73 , H01L29/739 , H01L29/06 , H01L29/10 , H01L29/423
CPC classification number: H01L29/7397 , H01L29/0634 , H01L29/1095 , H01L29/4236
Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
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公开(公告)号：US10923583B2
公开(公告)日：2021-02-16
申请号：US16601609
申请日：2019-10-15
Inventor： Zehong Li , Xin Peng , Yishang Zhao , Min Ren , Bo Zhang
IPC: H01L29/78 , H01L29/739 , H01L29/10 , H01L29/423
Abstract: The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability.
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公开(公告)号：US10135426B1
公开(公告)日：2018-11-20
申请号：US15960580
申请日：2018-04-24
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
IPC: H03K3/012 , H03K17/041 , H03K17/16
Abstract: A gate charge and discharge adjustment regulating circuit for a gate control device belongs to the power electronics technology field. The switch control signal is connected to the control terminals of the four analog switches. The gate control signal is loaded on the gate of the correct field effect transistor under the action of the four analog switches to control the switching-on degree so as to achieve the purpose of adjusting the gate driving signal current, that is, regulating the gate charge and discharge currents of the gate control device to realize the change of the switching characteristics and conduction characteristics. The switch control signal is connected to the input terminal of the gate driving module to control the gate driving module to generate the gate driving signal.
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Patent Agency Ranking
公开(公告)号：US09905682B2
公开(公告)日：2018-02-27
申请号：US15372352
申请日：2016-12-07
Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA , INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Inventor： Jinping Zhang , Zehong Li , Jingxiu Liu , Min Ren , Bo Zhang , Zhaoji Li
IPC: H01L29/74 , H01L29/78 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L29/10 , H01L29/40 , H01L29/66 , H01L29/747
CPC classification number: H01L29/7424 , H01L21/02233 , H01L21/26586 , H01L21/3065 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/408 , H01L29/66325 , H01L29/66386 , H01L29/7394 , H01L29/747 , H01L29/78
Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.
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公开(公告)号：US10546951B2
公开(公告)日：2020-01-28
申请号：US15774291
申请日：2016-09-17
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
Inventor： Min Ren , Yuci Lin , Chi Xie , Zhiheng Su , Zehong Li , Jinping Zhang , Wei Gao , Bo Zhang
IPC: H01L29/78 , H01L29/423
Abstract: A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.
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公开(公告)号：US10158350B1
公开(公告)日：2018-12-18
申请号：US15960573
申请日：2018-04-24
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
Abstract: The double pulse generator of the level shifter circuit takes out the rising edge and falling edge of the pulse width modulation signal PWM_H and generates corresponding narrow pulse signals. The two narrow pulse signals respectively pass through the pulse shaper to control the two field effect transistors in the switching circuit. The pulse width of the narrow pulse signal is not enough to completely switch on the two field effect transistors, so the generated waveform is a sawtooth wave; the drains of the two field effect transistors are respectively connected to the hysteresis-adjustable Schmidt trigger to restore the narrow pulse signal to the rising edge and falling edge pulse signal of the pulse width modulation signal PWM_HS with respect to the floating side VS, and then the signal is restored to the level-shifted pulse width modulation signal PWM HS after passing through the RS latch.
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8.发明授权公开(公告)号：US10056452B2
公开(公告)日：2018-08-21
申请号：US15197701
申请日：2016-06-29
Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA , ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Inventor： Zehong Li , Wenlong Song , Xunyi Song , Hongming Gu , Youbiao Zou , Jinping Zhang , Bo Zhang
IPC: H01L29/06 , H01L29/66 , H01L29/78 , H01L21/263 , H01L21/265 , H01L29/739 , H01L29/08 , H01L29/10 , H01L21/324
CPC classification number: H01L29/0634 , H01L21/263 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0878 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802
Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.
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公开(公告)号：US09929285B2
公开(公告)日：2018-03-27
申请号：US15602107
申请日：2017-05-23
IPC: H01L29/76 , H01L29/872 , H01L29/15 , H01L29/66
CPC classification number: H01L29/872 , H01L21/26586 , H01L29/0619 , H01L29/0634 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/66143
Abstract: The present invention relates to the field of semiconductor technology, particularly to a super-junction schottky diode. According to the present invention, the effective area of schottky junction is increased by forming the schottky junction in the trench located in the body of the device. Therefore, the current capacity of this novel schottky diode can be greatly improved. In addition, a super-junction structure is used to improve the device's reverse breakdown voltage and reduce the reverse leakage current. The super-junction schottky diode provided in the present invention can achieve a larger forward current, a lower on-resistance and a better reverse breakdown characteristic.
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