公开(公告)号：US08723262B2

公开(公告)日：2014-05-13

申请号：US13606893

申请日：2012-09-07

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。

公开(公告)号：US20140087526A1

公开(公告)日：2014-03-27

申请号：US13628251

申请日：2012-09-27

申请人： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity.

摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底绝缘体层上图形化半导体鳍片，将衬底绝缘体层布置在衬底上，在鳍片的一部分上构图虚拟栅极堆叠，形成与虚拟栅极叠层相邻的间隔区， 去除虚拟栅极堆叠以形成露出衬底绝缘体层和鳍的部分的空腔，去除衬底绝缘体层的暴露部分以增加空腔的深度，从衬底下方去除衬底绝缘体层的区域到 悬挂在衬底绝缘体层上方的鳍片的一部分，在空腔中形成栅极叠层，去除空腔中的栅极叠层的一部分以暴露布置在鳍片上的电介质层的一部分，并将绝缘体材料沉积在 腔。

公开(公告)号：US20130175594A1

公开(公告)日：2013-07-11

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

公开(公告)号：US20140027831A1

公开(公告)日：2014-01-30

申请号：US13570379

申请日：2012-08-09

申请人： Veeraraghavan S. Basker ,  Sivananda Kanakasabapathy ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Sivananda Kanakasabapathy ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/088

CPC分类号： H01L27/10867 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1211

摘要： The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

摘要翻译： 说明书和附图提出了一种新的方法，设备和计算机/软件相关产品（例如，计算机可读存储器），用于实现Fin FET器件结构中的eDRAM带形成。 提供了在第一半导体层和第二半导体层之间至少包括绝缘体层的半导体绝缘体（SOI）衬底。 （金属）带形成是通过在第二半导体层（Si）的鳍部分上沉积导电层和延伸到第二半导体层的每个DT电容器中的半导体材料（多晶硅）来实现的。 金属带由氮化物间隔物密封，以防止PWL和DT电容器之间的短路。

公开(公告)号：US08445334B1

公开(公告)日：2013-05-21

申请号：US13330746

申请日：2011-12-20

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。

公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

公开(公告)号：US08455313B1

公开(公告)日：2013-06-04

申请号：US13617709

申请日：2012-09-14

申请人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/41791 ,  H01L29/66795

摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.

摘要翻译： 提供了一种用于制造finFET器件的方法。 翅片结构形成在BOX层上。 翅片结构包括半导体层并沿第一方向延伸。 栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极。 栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。 植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。 虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。 硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

公开(公告)号：US20140054705A1

公开(公告)日：2014-02-27

申请号：US13595477

申请日：2012-08-27

申请人： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A fin field effect transistor (finFET) device includes a substrate; first and second source/drain regions located on the substrate; and a fin located on the substrate between the first and second source/drain regions. The fin includes a silicon germanium channel region and first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region. The first silicon buffer region is located between the first source/drain region and the silicon germanium channel region and the second silicon buffer region is located between the second source/drain region and the silicon germanium channel region.

摘要翻译： 鳍状场效应晶体管（finFET）器件包括衬底; 位于基板上的第一和第二源极/漏极区域; 以及位于第一和第二源极/漏极区域之间的衬底上的翅片。 散热片包括硅锗通道区域和位于与硅锗通道区域的任一侧相邻并且在硅锗通道区域上的翅片中的第一和第二硅缓冲区。 第一硅缓冲区位于第一源/漏区和硅锗沟道区之间，第二硅缓冲区位于第二源极/漏极区和硅锗沟道区之间。

公开(公告)号：US08637931B2

公开(公告)日：2014-01-28

申请号：US13337874

申请日：2011-12-27

申请人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

IPC分类号： H01L27/12

CPC分类号： H01L29/41791 ,  H01L29/66795

摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

摘要翻译： 提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于 翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。 翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。 硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

公开(公告)号：US20130154005A1

公开(公告)日：2013-06-20

申请号：US13606893

申请日：2012-09-07

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/12

CPC分类号： H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SW substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括：向SW基板提供翅片，在翅片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并翅片，在栅极周围沉积虚拟间隔物，以及将合并的外延膜 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。