公开(公告)号：US07716504B2

公开(公告)日：2010-05-11

申请号：US11457172

申请日：2006-07-13

申请人： Vijay B. Nijhawan ,  Alok Pant

发明人： Vijay B. Nijhawan ,  Alok Pant

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3228

摘要： A method for adjusting power management setting of the operating system while the system is in a sleep state. When a user attaches or removes power to the information handling system while the system is in a standby mode of operation, the sleep state system generates a wakeup event. During the resume process, the operating system checks a current power state of the information handling system and compares the current power state to the power state settings present when the information handling system entered the sleep state, resets the power state settings if necessary and then causes the information handling system to reenter the sleep state.

摘要翻译： 一种在系统处于睡眠状态时调整操作系统的电源管理设置的方法。 当用户在系统处于待机操作模式时附加或移除信息处理系统的电力时，睡眠状态系统产生唤醒事件。 在恢复过程中，操作系统检查信息处理系统的当前功率状态，并将当前功率状态与当信息处理系统进入休眠状态时存在的功率状态设置进行比较，如果需要，则重置电源状态设置，然后导致 信息处理系统重新进入睡眠状态。

公开(公告)号：US09207745B2

公开(公告)日：2015-12-08

申请号：US14340328

申请日：2014-07-24

申请人： Vijay B. Nijhawan ,  Gregory N. Darnell ,  Wuxian Wu

发明人： Vijay B. Nijhawan ,  Gregory N. Darnell ,  Wuxian Wu

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F11/34 ,  G06F11/00 ,  G06F9/48

CPC分类号： G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/329 ,  G06F9/4806 ,  G06F11/00 ,  G06F11/3017 ,  G06F11/3409 ,  G06F2201/81 ,  G06F2201/86 ,  Y02D10/126 ,  Y02D10/34

摘要： A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

摘要翻译： 公开了一种在采用平衡完全多线程负载阈值的信息处理系统（IHS）中管理处理器的性能和功率利用的方法。 该方法包括在处理器的所有当前线程利用率中提供最大当前线程利用率（Umax）和最小当前线程利用率（Umin），并确定处理器的当前性能状态（P状态）。 该方法还包括当处理器的当前P状态在Umax和Umin之间时将处理器的当前P状态增加到处理器的下一个P状态朝向处理器的最大P状态（Pmax），并且当前利用率 处理器小于第一阈值利用率。 该方法还包括当处理器的当前P状态达到Pmax并且处理器的当前利用率大于处理器的第一阈值利用率时，以turbo模式接合处理器。

公开(公告)号：US10055357B2

公开(公告)日：2018-08-21

申请号：US15058754

申请日：2016-03-02

申请人： Sumanth Vidyadhara ,  Vijay B. Nijhawan

发明人： Sumanth Vidyadhara ,  Vijay B. Nijhawan

IPC分类号： G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F21/57 ,  G06F12/1027

CPC分类号： G06F12/1081 ,  G06F12/0292 ,  G06F12/1027 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/42 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/034

摘要： Systems and methods are provided that may be implemented to systems and methods that may be implemented to utilize direct memory access (DMA) remapping to control firmware updates and/or other configuration changes or device access control protocol for devices of an information handling system during the Unified Extensible Firmware Interface (UEFI) pre-boot phase before the booting the operating system (OS). The disclosed systems and methods may use DMA remapping during UEFI pre-boot to determine whether to allow or disallow pre-boot firmware updates and/or device configuration for hardware devices, and may be performed in the presence or absence of UEFI Secure Boot.

公开(公告)号：US20170255567A1

公开(公告)日：2017-09-07

申请号：US15058754

申请日：2016-03-02

申请人： Sumanth Vidyadhara ,  Vijay B. Nijhawan

发明人： Sumanth Vidyadhara ,  Vijay B. Nijhawan

IPC分类号： G06F12/10 ,  G06F21/57 ,  G06F13/42 ,  G06F13/16 ,  G06F13/28

CPC分类号： G06F12/1081 ,  G06F12/0292 ,  G06F12/1027 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/42 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/034

摘要： Systems and methods are provided that may be implemented to systems and methods that may be implemented to utilize direct memory access (DMA) remapping to control firmware updates and/or other configuration changes or device access control protocol for devices of an information handling system during the Unified Extensible Firmware Interface (UEFI) pre-boot phase before the booting the operating system (OS). The disclosed systems and methods may use DMA remapping during UEFI pre-boot to determine whether to allow or disallow pre-boot firmware updates and/or device configuration for hardware devices, and may be performed in the presence or absence of UEFI Secure Boot.

公开(公告)号：US06697920B2

公开(公告)日：2004-02-24

申请号：US10057861

申请日：2002-01-24

申请人： Vijay B. Nijhawan ,  Hon Fei Chong

发明人： Vijay B. Nijhawan ,  Hon Fei Chong

IPC分类号： G06F1206

CPC分类号： G06F9/5016 ,  G06F9/4401

摘要： A memory manager, method and computer system that allows use of Extended Upper Memory Block (XUMB) memory space by system BIOS to store runtime code and data. In an exemplary memory manager, BIOS Power-On-Self-Test (POST) code sets up or allocates 1 the XUMB memory space at TP_SETUP_WAD (0D3h). The BIOS code finds space for the XUMB memory space in an extended memory space. The BIOS code then zeroes out the XUMB memory space and stores the address of the XUMB memory space in a variable. When different components of the BIOS code need to reserve memory in the XUMB memory space, they call a predetermined calling function. The calling function reserves memory for each of the different components in the XUMB memory space and allocates pointers to the specific addresses that may be used by these components. The BIOS components then copy their own data into these memory locations of the XUMB memory space.

摘要翻译： 内存管理器，方法和计算机系统，允许系统BIOS使用扩展的高内存块（XUMB）内存空间来存储运行时代码和数据。 在示例性存储器管理器中，BIOS自检自检（POST）代码在TP_SETUP_WAD（0D3h）处建立或分配1个XUMB存储器空间。 BIOS代码为扩展内存空间中的XUMB内存空间找到空间。 然后，BIOS代码将XUMB内存空间清零，并将XUMB内存空间的地址存储在变量中。 当BIOS代码的不同组件需要在XUMB存储空间中保留内存时，它们调用预定的调用功能。 调用函数为XUMB存储空间中的每个不同组件预留内存，并分配指向这些组件可能使用的特定地址的指针。 然后，BIOS组件将自己的数据复制到XUMB内存空间的这些内存位置。

公开(公告)号：US07577813B2

公开(公告)日：2009-08-18

申请号：US11247036

申请日：2005-10-11

申请人： Vijay B. Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

发明人： Vijay B. Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

IPC分类号： G06F12/00

CPC分类号： G06F12/0806 ,  G06F9/5016 ,  G06F2212/2542

摘要： A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

摘要翻译： 公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。 使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。 处理系统。 然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。 信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

公开(公告)号：US07500067B2

公开(公告)日：2009-03-03

申请号：US11392272

申请日：2006-03-29

申请人： Madhusudhan Rangarajan ,  Vijay B. Nijhawan

发明人： Madhusudhan Rangarajan ,  Vijay B. Nijhawan

IPC分类号： G06F12/00

CPC分类号： G06F12/0646 ,  G06F12/0806 ,  G06F2212/2542

摘要： The present disclosure describes systems and methods for allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distribute shared memory. The systems and methods include allocating memory to input-output devices (I/O devices) based at least in part on which memory resource is physically closest to a particular I/O device. Through these systems and methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory to an I/O device that i80s on the same node as a memory resource, reduces memory access time thereby maximizing data transmission. The present disclosure further describes a system and method for improving performance in a multiprocessor computer system by utilizing a pre-programmed device affinity table. The system and method includes listing the memory resources physically closest to each I/O device and accessing the device table to determine the closest memory resource to a particular I/O device. The system and method further includes directing a device driver to transmit data between the I/O device and the closest memory resource.

摘要翻译： 本公开描述了在诸如具有分发共享存储器的不均匀存储器访问（NUMA）机器的多处理器计算机系统中分配存储器的系统和方法。 所述系统和方法包括至少部分地基于哪个存储器资源物理上最接近于特定I / O设备而将存储器分配给输入输出设备（I / O设备）。 通过这些系统和方法，在NUMA机器中更有效地分配存储器。 例如，将内存分配给与存储器资源相同的节点上的i80的I / O设备，从而减少存储器访问时间，从而最大化数据传输。 本公开进一步描述了通过利用预编程的设备亲和度表来改善多处理器计算机系统中的性能的系统和方法。 系统和方法包括列出物理上最接近每个I / O设备的存储器资源并访问设备表以确定到特定I / O设备的最近的存储器资源。 该系统和方法还包括引导设备驱动器在I / O设备和最接近的存储器资源之间传输数据。