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    Multi-phase interpolators and related methods
    1.
    发明授权
    Multi-phase interpolators and related methods 有权
    多相内插器及相关方法

    公开(公告)号：US08294500B1

    公开(公告)日：2012-10-23

    申请号：US12621493

    申请日：2009-11-18

    申请人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang ,  Van Ton-That

    发明人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang ,  Van Ton-That

    IPC分类号： H03H11/16

    CPC分类号： G06G7/30

    摘要： A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

    摘要翻译： 相位插值器电路包括耦合以形成差分对的第一和第二晶体管，负载电路，第一组开关电路，第二组开关电路和电流源。 第一组开关电路耦合在第一晶体管和负载电路之间。 第二组开关电路耦合在第二晶体管和负载电路之间。 电流源为差分对提供电流。

    Multi-purpose phase-locked loop for low cost transceiver
    2.
    发明授权
    Multi-purpose phase-locked loop for low cost transceiver 有权
    用于低成本收发器的多功能锁相环

    公开(公告)号：US08619931B1

    公开(公告)日：2013-12-31

    申请号：US12622152

    申请日：2009-11-19

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H04L7/002

    摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

    摘要翻译： 提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。 一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

    Techniques for phase interpolation
    3.
    发明授权
    Techniques for phase interpolation 有权
    相位插值技术

    公开(公告)号：US07994837B1

    公开(公告)日：2011-08-09

    申请号：US12537634

    申请日：2009-08-07

    申请人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang

    发明人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang

    IPC分类号： H03H11/16

    CPC分类号： H03H11/22

    摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

    摘要翻译： 相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路 负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。 相位内插器电路可以包括三个差分对的晶体管。 具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。 相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

    Phase-locked loop architecture and clock distribution system
    4.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08228102B1

    公开(公告)日：2012-07-24

    申请号：US12717062

    申请日：2010-03-03

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条 侧。 可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。 另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。 每个PMA三元组模块包括第一，第二和第三通道。 第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。 还公开了其它实施例和特征。

    Techniques for generating fractional periodic signals
    5.
    发明授权
    Techniques for generating fractional periodic signals 有权
    产生分数周期信号的技术

    公开(公告)号：US08537956B1

    公开(公告)日：2013-09-17

    申请号：US12954514

    申请日：2010-11-24

    申请人： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

    发明人： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0802 ,  H03L7/1976 ,  H04J3/047 ,  H04J3/062

    摘要： A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

    摘要翻译： 解复用器电路将具有不同数据速率的输入数据分离成输出数据。 锁相环电路产生具有基于第二时钟信号的频率的平均频率乘以分数非整数的第一时钟信号。 串行器电路串行化一组输出数据以响应于由锁相环电路产生的第一时钟信号之一产生串行数据信号。

    Phase-locked loop architecture and clock distribution system
    8.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08542042B1

    公开(公告)日：2013-09-24

    申请号：US13532528

    申请日：2012-06-25

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    摘要： One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

    Carry circuit with power-save mode
    9.
    发明授权
    Carry circuit with power-save mode 有权
    带省电模式的携带电路

    公开(公告)号：US07436208B1

    公开(公告)日：2008-10-14

    申请号：US11487916

    申请日：2006-07-17

    申请人： Tien Duc Pham

    发明人： Tien Duc Pham

    IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/0175

    CPC分类号： H03K19/17784 ,  H03K19/17728

    摘要： A carry circuit having a power-save mode and a method for reducing power consumption of an integrated circuit are described. A power-save input is selected for control select signaling. A voltage level input is selected as an initial carry input. The initial carry input is propagated through a carry stage responsive to the carry input and the control select signaling. The carry stage is placed in a first non-switching steady state mode responsive to the propagating of the initial carry input through the carry stage.

    摘要翻译： 描述了具有省电模式的携带电路和用于降低集成电路的功耗的方法。 为控制选择信号选择省电输入。 选择电压电平输入作为初始进位输入。 响应于进位输入和控制选择信号，初始进位输入通过进位级传播。 响应于通过进位级的初始进位输入的传播，进位级被置于第一非切换稳态模式。