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    NETWORK COMPUTER SYSTEMS WITH POWER MANAGEMENT
    4.
    发明申请
    NETWORK COMPUTER SYSTEMS WITH POWER MANAGEMENT 审中-公开
    具有电源管理的网络计算机系统

    公开(公告)号：US20160342195A1

    公开(公告)日：2016-11-24

    申请号：US15092492

    申请日：2016-04-06

    申请人： Virident Systems, Inc.

    发明人： Vijay Karamcheti ,  Kenneth Alan Okin ,  Kumar Ganapathy

    IPC分类号： G06F1/32 ,  G06F3/06

    CPC分类号： G06F1/329 ,  G06F1/3209 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0674 ,  G06F3/0689 ,  G06F9/5094 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

    摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储装置。 存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。 存储器阵列是块读/写可访问和随机读取可访问的。 块读/写控制器耦合在存储器阵列和外部互连之间。 块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。 随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。 随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

    MEMORY CHANNEL CONNECTED NON-VOLATILE MEMORY
    5.
    发明申请
    MEMORY CHANNEL CONNECTED NON-VOLATILE MEMORY 有权
    内存通道连接的非易失性存储器

    公开(公告)号：US20140379969A1

    公开(公告)日：2014-12-25

    申请号：US14475398

    申请日：2014-09-02

    申请人： Virident Systems, Inc.

    发明人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F13/12 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/25 ,  G06F2212/7203 ,  G11C7/1006 ,  G11C7/1072 ,  Y02D10/14

    摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

    摘要翻译： 一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在与多个印刷电路板迹线中的一个或多个印刷电路板迹线耦合的印刷电路板上的存储器控​​制器，多个非易失型存储器集成电路 耦合到印刷电路板，以及耦合在存储器控制器和多个非易失性类型的存储器集成电路之间的多个支持集成电路。

    FRONT/BACK CONTROL OF INTEGRATED CIRCUITS FOR FLASH DUAL INLINE MEMORY MODULES
    6.
    发明申请
    FRONT/BACK CONTROL OF INTEGRATED CIRCUITS FOR FLASH DUAL INLINE MEMORY MODULES 有权
    用于闪存双内存模块的集成电路的前/后控制

    公开(公告)号：US20160254061A1

    公开(公告)日：2016-09-01

    申请号：US15133217

    申请日：2016-04-19

    申请人： Virident Systems, Inc.

    发明人： Ruban Kanapathippillai ,  Kenneth Alan Okin

    IPC分类号： G11C16/30 ,  H01R12/72 ,  H05K1/02 ,  H05K1/18

    CPC分类号： G11C16/30 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H01R12/725 ,  H05K1/0286 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49169

    摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

    摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装数量，并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。