公开(公告)号：US5492865A

公开(公告)日：1996-02-20

申请号：US314425

申请日：1994-09-28

申请人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

发明人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L23/291 ,  H01L21/314 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/91 ,  Y10S438/958

摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

摘要翻译： 本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。 非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

公开(公告)号：US5374833A

公开(公告)日：1994-12-20

申请号：US775085

申请日：1991-10-11

申请人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

发明人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H02L45/00

CPC分类号： H01L23/291 ,  H01L21/314 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/91 ,  Y10S438/958

摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

摘要翻译： 本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。 非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

公开(公告)号：US5602056A

公开(公告)日：1997-02-11

申请号：US434528

申请日：1995-05-04

申请人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

发明人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H01L21/44

CPC分类号： H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/314 ,  H01L21/31612 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

摘要翻译： 本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。 根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。 用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。 用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。 在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

公开(公告)号：US5763937A

公开(公告)日：1998-06-09

申请号：US277090

申请日：1994-07-19

申请人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

发明人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

IPC分类号： H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L27/115 ,  H01L29/78 ,  H01L23/58

CPC分类号： H01L29/6659 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/314 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

摘要翻译： 本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。 根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。 用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。 用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。 在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

公开(公告)号：US5328865A

公开(公告)日：1994-07-12

申请号：US11084

申请日：1993-01-29

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

摘要翻译： 一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

公开(公告)号：US5290734A

公开(公告)日：1994-03-01

申请号：US736162

申请日：1991-07-26

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的衬底上的氧化物层，设置在开口内并接触衬底的非晶硅材料，设置在非晶态上的导电保护材料，例如钛钨 硅材料和衬在保护材料内形成的凹部的壁上的氧化物间隔物。 保护材料和间隔物为反熔丝结构提供更严格的编程电压分布，并有助于防止反熔丝故障。

公开(公告)号：US5120679A

公开(公告)日：1992-06-09

申请号：US710220

申请日：1991-06-04

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的基底上的氧化物层，设置在开口内并接触基底的非晶硅材料以及衬在非晶硅内形成的凹陷壁的氧化物间隔物 。 间隔物通过覆盖形成在非晶硅材料中的尖头来防止抗熔丝结构的故障。 本发明的方法形成上述反熔丝结构，并且进一步解决了从抗熔丝结构位置之外的区域去除不想要的隔离材料的问题。

公开(公告)号：USRE36893E

公开(公告)日：2000-10-03

申请号：US795098

申请日：1997-02-06

申请人： Dipankar Pramanik ,  Subhash R. Nariani

发明人： Dipankar Pramanik ,  Subhash R. Nariani

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L23/48 ,  H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

摘要翻译： 根据本发明形成的抗熔丝结构包括导电层基底。 一层抗熔丝材料覆盖在导电基层上。 在抗熔丝层的顶部是绝缘层，其中在反熔丝层上形成通孔。 通孔的横向尺寸小于约0.8微米。 在通孔中设置有导电非Al插塞，其包括诸如TiN或TiW的导电阻挡材料以接触抗熔丝材料并覆盖在绝缘层上。 钨被有效地用作非铝插头。 导电层形成在插塞上方，并且与抗熔丝层分开至少通孔深度的二分之一。 然后通过施加编程电压可编程结构，并通过施加低于编程电压的感测电压来读取结构。

公开(公告)号：US5573970A

公开(公告)日：1996-11-12

申请号：US477311

申请日：1995-06-06

申请人： Dipankar Pramanik ,  Subhash R. Nariani

发明人： Dipankar Pramanik ,  Subhash R. Nariani

IPC分类号： H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

摘要翻译： 根据本发明形成的抗熔丝结构包括导电层基底。 一层抗熔丝材料覆盖在导电基层上。 在抗熔丝层的顶部是绝缘层，其中在反熔丝层上形成通孔。 通孔的横向尺寸小于约0.8微米。 在通孔中设置有导电性非铝塞，其覆盖与导电阻挡材料（例如TiN或TiW）接触反熔丝材料并覆盖绝缘层的层。 钨被有效地用作非铝插头。 导电层形成在插塞上方，并且通过插头与覆盖抗熔丝层的导电阻挡材料分离。 然后通过施加编程电压可编程结构，并通过施加低于编程电压的感测电压来读取结构。

公开(公告)号：US5128279A

公开(公告)日：1992-07-07

申请号：US776503

申请日：1991-10-11

申请人： Subhash R. Nariani ,  Dipankar Pramanik

发明人： Subhash R. Nariani ,  Dipankar Pramanik

IPC分类号： H01L23/29 ,  H01L23/532 ,  H01L27/115

CPC分类号： H01L23/291 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/958

摘要： Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

摘要翻译： 在MOS结构中寄生泄漏最小化。 集成电路晶片包括通过第一级金属化施加的常规MOS元件。 金属间电介质包括三层，用于平坦化的中间有机玻璃层和上部和下部氧化物层。 在电介质上施加第二金属化。 钝化包括较低的氧化物钝化和上部氮化物钝化。 来自氮化物钝化的氢迁移到有机玻璃中并形成诱发寄生泄漏的正电荷。 金属间电介质中的低氧化物层是富含硅的，以提供悬挂键，其中和这种电荷形成，从而最小化寄生泄漏。