公开(公告)号：US20050035799A1

公开(公告)日：2005-02-17

申请号：US10944136

申请日：2004-09-16

申请人： Vladimir Mikhalev ,  Aaron Schoenfeld ,  Daniel Penney ,  William Waldrop

发明人： Vladimir Mikhalev ,  Aaron Schoenfeld ,  Daniel Penney ,  William Waldrop

IPC分类号： G11C7/10 ,  H03L7/081 ,  H03L7/06

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  H03L7/0812

摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

摘要翻译： 延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。 时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。 响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。 延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。

公开(公告)号：US20070008758A1

公开(公告)日：2007-01-11

申请号：US11177540

申请日：2005-07-08

申请人： William Waldrop

发明人： William Waldrop

IPC分类号： G11C19/08

CPC分类号： G11C7/1072 ,  G11C7/222

摘要： A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such variable delays, is disclosed. In one embodiment, a first time domain as specified by an internal clock is delayed by the propagation delay of the read decoder block plus the propagation delay of the output circuitry via a model to create a second time domain which lags the first time domain. Processing in the second time domain associates the internal read command with a particular external clock cycle, and accounts for the specified read latency of the device. The output of such second time domain processing is a signal indicative of which external cycle should be used to enable the outputs. This signal is then converted back into the first timing domain by latches which lead the second timing domain.

摘要翻译： 公开了一种用于减轻可变读取解码传播延迟和可变输出电路传播延迟对读取等待时间的不利影响的方法和电路，并且具体地用于根据这种可变延迟在适当的时间产生输出使能信号。 在一个实施例中，由内部时钟指定的第一时域被读取解码器块的传播延迟加上输出电路经由模型的传播延迟延迟，以产生滞后第一时域的第二时域。 第二时域中的处理将内部读取命令与特定的外部时钟周期相关联，并考虑了设备的指定读取延迟。 这种第二时域处理的输出是指示应该使用哪个外部周期来使能输出的信号。 然后，该信号通过引导第二定时域的锁存器转换回第一定时域。

公开(公告)号：US20050068071A1

公开(公告)日：2005-03-31

申请号：US10983455

申请日：2004-11-08

申请人： William Waldrop

发明人： William Waldrop

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03B1/00

CPC分类号： H04L25/028 ,  H03K19/00315 ,  H03K19/018585 ,  H04L25/085

摘要： An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

摘要翻译： 讨论了包括具有用于驱动数据总线的两种操作模式的数据输出驱动器的集成电路器件。 输出驱动器包括产生全驱动输出高信号，部分驱动输出高信号，全驱动输出低信号和部分驱动输出低信号的电路。 输出驱动器可以防止数据总线上的负电压。 输出驱动器是可选择的，适用于驱动端接负载和未终端负载。

公开(公告)号：US20070030030A1

公开(公告)日：2007-02-08

申请号：US11195897

申请日：2005-08-03

申请人： William Waldrop

发明人： William Waldrop

IPC分类号： H03K19/00

CPC分类号： H04L25/0278 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 操作诸如存储器芯片的电子设备的系统和方法具有被配置为包括ODT（片上终端）模式检测器的输出驱动器电路，检测是否存在足够的可用于操作ODT部分的内部时钟 输出驱动器处于同步操作模式或将操作切换到异步模式。 基于时钟的内部ODT操作模式（同步与异步）的确定避免了输出驱动器中ODT控制单元中复杂且不灵活的时钟处理逻辑的使用。 这使得能够在各种设备操作模式（例如，有功，掉电等）期间对ODT电路的实际时钟进行改变，而不需要为这些模式中的每一个重新设计ODT控制逻辑。 ODT模式检测器设计的简单性和灵活性允许有效地利用芯片的不动产而不影响电子设备中输出驱动器的信号传输速度。 由于管理摘要的规则，本摘要不应用于解释索赔。