公开(公告)号：US20070292996A1

公开(公告)日：2007-12-20

申请号：US11846544

申请日：2007-08-29

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthler ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthler ,  Jed Rankin ,  William Tonti

IPC分类号： H01L21/84

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

摘要翻译： 公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

公开(公告)号：US20070170521A1

公开(公告)日：2007-07-26

申请号：US11306827

申请日：2006-01-12

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070127172A1

公开(公告)日：2007-06-07

申请号：US11275058

申请日：2005-12-06

申请人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

IPC分类号： H02H9/00

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。 不需要额外的引脚。

公开(公告)号：US20070284669A1

公开(公告)日：2007-12-13

申请号：US11838934

申请日：2007-08-15

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20050186744A1

公开(公告)日：2005-08-25

申请号：US10785895

申请日：2004-02-24

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6659

摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

公开(公告)号：US20060091951A1

公开(公告)日：2006-05-04

申请号：US10904238

申请日：2004-10-29

申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

IPC分类号： H03F3/45 ,  H03F3/16

CPC分类号： H03F3/16 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45468

摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.

摘要翻译： 在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。 隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

公开(公告)号：US20060157799A1

公开(公告)日：2006-07-20

申请号：US10905682

申请日：2005-01-17

申请人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

发明人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L27/027

摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。

公开(公告)号：US08884270B2

公开(公告)日：2014-11-11

申请号：US13436159

申请日：2012-03-30

申请人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

发明人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

IPC分类号： H01L29/06 ,  H01L29/808 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/8083 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/66909

摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.

摘要翻译： 描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。 电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

公开(公告)号：US20050227418A1

公开(公告)日：2005-10-13

申请号：US10708912

申请日：2004-03-31

申请人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

发明人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

IPC分类号： H01L21/329 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66136 ,  H01L29/861

摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

摘要翻译： 一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层 结构体; 并移除保护结构。 该方法还包括在扩散区上形成硅化物层并与保护结构对准。 保护结构包括硬掩模，其中硬掩模包括氮化硅层。 或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。 此外，在去除步骤中，衬垫保留在衬底上。

公开(公告)号：US20070249069A1

公开(公告)日：2007-10-25

申请号：US11410883

申请日：2006-04-25

申请人： David Alvarez ,  Kiran Chatty ,  Cornelius Russ

发明人： David Alvarez ,  Kiran Chatty ,  Cornelius Russ

IPC分类号： H01L21/66

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L22/12

摘要： A method of manufacturing a semiconductor device includes providing a workpiece comprising a plurality of active areas, and analyzing the active areas to determine desired stress levels for each active area. The method includes determining at least one first active area to have a first amount of stress and at least one second active area to have a second amount of stress. A stress-controlling material is formed over the at least one second active area, but not over the at least one first active area. A stress-increasing material is formed over the at least one first active area and over the stress-controlling material that is over the at least one second active area.

摘要翻译： 制造半导体器件的方法包括提供包括多个有效区域的工件，以及分析有效区域以确定每个有效区域的期望的应力水平。 该方法包括确定至少一个第一有效区域具有第一应力量和至少一个第二有效区域以具有第二应力量。 应力控制材料形成在至少一个第二有效区域上，但不在至少一个第一有效区域上。 在所述至少一个第一有效区域上并且超过所述至少一个第二有效区域上的所述应力控制材料上形成应力增加材料。