公开(公告)号：US08572426B2

公开(公告)日：2013-10-29

申请号：US12802020

申请日：2010-05-27

申请人： Wai Cheong Chan ,  Matthew J. Schade

发明人： Wai Cheong Chan ,  Matthew J. Schade

IPC分类号： G06F1/00

CPC分类号： G06F1/3296 ,  Y02D10/172

摘要： An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

摘要翻译： 一种装置包括具有至少两个平行分支的延迟线，其中每个分支包括串联耦合的多个延迟单元。 延迟线被配置为接收输入信号并且通过分支中的延迟单元并行地传播输入信号。 该装置还包括多个采样电路，其被配置为在延迟线的分支中的不同抽头处采样输入信号并输出​​采样值。 与第二个分支中的抽头相比，第一个分支中的抽头与不同的延迟量相关联。 延迟线的分支中的至少一些延迟单元可以具有最小延迟，并且第一分支中的至少一个抽头与第二分支中的至少一个抽头之间的延迟差可以小于 最小延误。

公开(公告)号：US20110291729A1

公开(公告)日：2011-12-01

申请号：US12802020

申请日：2010-05-27

申请人： Wai Cheong Chan ,  Matthew J. Schade

发明人： Wai Cheong Chan ,  Matthew J. Schade

IPC分类号： H03H11/26

CPC分类号： G06F1/3296 ,  Y02D10/172

摘要： An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

摘要翻译： 一种装置包括具有至少两个平行分支的延迟线，其中每个分支包括串联耦合的多个延迟单元。 延迟线被配置为接收输入信号并且通过分支中的延迟单元并行地传播输入信号。 该装置还包括多个采样电路，其被配置为在延迟线的分支中的不同抽头处采样输入信号并输出​​采样值。 与第二个分支中的抽头相比，第一个分支中的抽头与不同的延迟量相关联。 延迟线的分支中的至少一些延迟单元可以具有最小延迟，并且第一分支中的至少一个抽头与第二分支中的至少一个抽头之间的延迟差可以小于 最小延误。

公开(公告)号：US07149903B1

公开(公告)日：2006-12-12

申请号：US10324997

申请日：2002-12-18

申请人： Wai Cheong Chan ,  Donald Kevin Cameron

发明人： Wai Cheong Chan ,  Donald Kevin Cameron

IPC分类号： G06F1/26 ,  H03K27/00

CPC分类号： H03K27/00

摘要： A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

摘要翻译： 一种用于逻辑集成电路中的松弛确定的系统和方法。 一个启动脉冲被输入到一个循环延迟回路中。 发射脉冲的前沿使得脉冲在环形延迟环周围循环。 通过循环脉冲循环进行的通过次数由锁存/计数器电路计数。 采样脉冲被输入到锁存/计数器电路以锁存在采样脉冲的前沿的脉冲循环数。 脉冲循环计数提供电路中的延迟信息，其随后可用于调整集成电路中的电源电压。

公开(公告)号：US06353346B1

公开(公告)日：2002-03-05

申请号：US09684754

申请日：2000-10-06

申请人： Wai Cheong Chan

发明人： Wai Cheong Chan

IPC分类号： H03B100

CPC分类号： H03K19/018585 ,  H03K3/3565 ,  H03K17/167 ,  H03K19/00361

摘要： An adaptive output driver that uses a programmable Schmitt-trigger buffer to change the driver's operational response after it is manufactured. The adaptive output driver includes a primary driver that provides the primary current to drive an output signal into a load. A secondary driver for the adaptive output driver is enabled by the Schmitt-trigger buffer to provide an additional current to drive the load when the transitions between high and low states are slower than a predetermined slew rate. The programmable Schmitt-trigger buffer includes cells of pull-up and pull-down transistors that can be separately enabled. Each enabled cell causes an imbalance in the overall sizing ratio of activated pull-up and pull-down transistors; the amount of imbalance in the overall sizing ratio corresponds to the amount of hysteresis in the response of the Schmitt-trigger buffer. By programming the amount of hysteresis in the Schmitt-trigger buffer, the operation of the adaptive output driver can be modified to suit different loading conditions after manufacture. The programmable Schmitt-trigger buffer can be used in the input stage of an input/output driver employed with a microprocessor. Also, the programmable Schmitt-trigger buffer may be used with a distributed and weighted output driver to provide separate delays in the operation of selected output stages.

摘要翻译： 自适应输出驱动器，使用可编程施密特触发缓冲器，在制造后改变驱动器的运行响应。 自适应输出驱动器包括主驱动器，其提供初级电流以将输出信号驱动到负载中。 自适应输出驱动器的辅助驱动器由施密特触发缓冲器启用，以便在高状态和低态之间的转换比预定转换速率慢时提供额外的电流来驱动负载。 可编程施密特触发缓冲器包括可单独使能的上拉和下拉晶体管单元。 每个使能的单元导致激活的上拉和下拉晶体管的整体尺寸比例的不平衡; 整体尺寸比例中的不平衡量对应于施密特触发缓冲器的响应中的滞后量。 通过对施密特触发缓冲器中的滞后量进行编程，可以修改自适应输出驱动器的操作，以适应不同的加载条件。 可编程施密特触发缓冲器可用于与微处理器一起使用的输入/输出驱动器的输入级。 此外，可编程施密特触发缓冲器可以与分布式和加权输出驱动器一起使用，以在选择的输出级的操作中提供单独的延迟。

公开(公告)号：US07069461B1

公开(公告)日：2006-06-27

申请号：US10351056

申请日：2003-01-24

申请人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

发明人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

IPC分类号： G06F1/04

CPC分类号： G11C5/14 ,  G11C7/1072 ,  G11C11/4074

摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

摘要翻译： 响应于时钟信号的频率的变化来调整存储器系统的电源电压。 存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。 当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。 改变电源电压的大小，将定时值返回到第一个值。

公开(公告)号：US06946881B1

公开(公告)日：2005-09-20

申请号：US10171571

申请日：2002-06-14

申请人： Wai Cheong Chan

发明人： Wai Cheong Chan

IPC分类号： G01R19/00 ,  G01R19/14 ,  H04N5/08

CPC分类号： H04N5/08 ,  G01R19/14 ,  G09G5/006 ,  G09G5/18

摘要： In a polarity detector circuit for detecting the polarity of monitor sync signals, a clock generator and counter circuit are provided to count clock cycles during the positive and negative portions of the signal. Comparators are used to compare the counter values to predetermined values to determine when one or both of the counters has reached a predefined value. With the proper choice of sampling clock, this digital implementation can be easily optimized for small size and simplicity.

摘要翻译： 在用于检测监视同步信号的极性的极性检测器电路中，提供时钟发生器和计数器电路以在信号的正和负部分期间计数时钟周期。 比较器用于将计数器值与预定值进行比较，以确定一个或两个计数器何时达到预定值。 通过适当选择采样时钟，可以轻松优化数字实现，以实现小尺寸和简单性。

公开(公告)号：US06710637B1

公开(公告)日：2004-03-23

申请号：US10134832

申请日：2002-04-29

申请人： Wai Cheong Chan

发明人： Wai Cheong Chan

IPC分类号： H03K3037

CPC分类号： H03K5/1515 ,  H03K5/00006 ,  H03K5/1534

摘要： In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

摘要翻译： 在提供两相时钟信号的非重叠时钟发生器电路中，使用存储器元件的时钟到Q延迟来定义非重叠时间。 可以以标准存储器元件的时钟到Q延迟的增量编程非重叠时间。

公开(公告)号：US07206959B1

公开(公告)日：2007-04-17

申请号：US10351061

申请日：2003-01-24

申请人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

发明人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/08 ,  Y02D10/126

摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

摘要翻译： 响应于时钟信号的频率的变化来调整存储器系统的电源电压。 存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。 当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。 改变电源电压的大小，将定时值返回到第一个值。

公开(公告)号：US06970015B1

公开(公告)日：2005-11-29

申请号：US10099586

申请日：2002-03-14

申请人： Wai Cheong Chan ,  Khusrow Kiani

发明人： Wai Cheong Chan ,  Khusrow Kiani

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/0175

CPC分类号： H03K17/167 ,  H03K19/0027

摘要： The invention enables the performance of the input and output stages of an I/O circuit to be modified after an IC is manufactured. In one embodiment, the I/O circuit includes an output driver, programmable pre-driver, programmable Schmitt-trigger input buffer, control circuit and logic circuit. Depending on the number of pull-up and pull-down MOS transistor pairs or “cells” that are enabled in the programmable pre-driver and their different sizes, the overall sizing ratio imbalance between the transistors may be programmed. In particular, the high and low trip points for activation of the output driver is related to an imbalance in the overall sizing ratio of transistors enabled in the programmable pre-driver. This affects the timing characteristics of the output driver.

摘要翻译： 本发明能够在制造IC之后对I / O电路的输入和输出级的性能进行修改。 在一个实施例中，I / O电路包括输出驱动器，可编程预驱动器，可编程施密特触发器输入缓冲器，控制电路和逻辑电路。 根据在可编程预驱动器中使能的上拉和下拉MOS晶体管对或“单元”的数量及其不同的尺寸，可以编程晶体管之间的整体尺寸比不平衡。 特别地，用于激活输出驱动器的高和低跳变点与在可编程预驱动器中启用的晶体管的整体尺寸比的不平衡有关。 这会影响输出驱动器的时序特性。

公开(公告)号：US06874933B1

公开(公告)日：2005-04-05

申请号：US10272354

申请日：2002-10-15

申请人： Wai Cheong Chan

发明人： Wai Cheong Chan

IPC分类号： G01K1/02 ,  G01K7/01 ,  G01K7/00

CPC分类号： G01K7/01 ,  G01K1/028

摘要： A circuit for measuring temperature with all digital components in an integrated circuit. During manufacture, the number of clock period cycles during a known period of time at a predetermined temperature is stored in non-volatile memory. Later, during use of the integrated circuit, a clock circuit is activated and each cycle of its period is counted during a known length of time. Using the previously saved number of clock circuit cycles at a predetermined temperature and a current count of clock cycles for another known length of time, the current period of the clock circuit can be calculated and used to determine the current temperature.

摘要翻译： 用于测量集成电路中所有数字组件的温度的电路。 在制造期间，在预定温度下的已知时间段内的时钟周期周期的数量被存储在非易失性存储器中。 之后，在集成电路的使用期间，激活时钟电路，并且在已知时间段内对其周期的每个周期进行计数。 在预定温度下使用先前保存的数量的时钟电路循环和另一个已知时间长度的时钟周期的当前计数，可以计算时钟电路的当前周期并用于确定当前温度。