Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
Abstract:
A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.
Abstract:
An interconnect for testing semiconductor components includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The interconnect can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.
Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
Abstract:
A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.
Abstract:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
Abstract:
Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.
Abstract:
A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.