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公开(公告)号：US20110233777A1
公开(公告)日：2011-09-29
申请号：US13154550
申请日：2011-06-07
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。
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公开(公告)号：US20100171217A1
公开(公告)日：2010-07-08
申请号：US12725724
申请日：2010-03-17
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
IPC分类号： H01L23/498
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。
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公开(公告)号：US20080111213A1
公开(公告)日：2008-05-15
申请号：US11924781
申请日：2007-10-26
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
IPC分类号： H01L23/488
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。
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公开(公告)号：US07300857B2
公开(公告)日：2007-11-27
申请号：US10932296
申请日：2004-09-02
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
IPC分类号： H01L21/441
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。
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公开(公告)号：US20060043599A1
公开(公告)日：2006-03-02
申请号：US10932296
申请日：2004-09-02
申请人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
发明人： Salman Akram , Charles Watkins , Mark Hiatt , David Hembree , James Wark , Warren Farnworth , Mark Tuttle , Sidney Rigg , Steven Oliver , Kyle Kirby , Alan Wood , Lu Velicky
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
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公开(公告)号：US07956443B2
公开(公告)日：2011-06-07
申请号：US12725724
申请日：2010-03-17
申请人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。
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7.发明授权Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件公开(公告)号：US07955946B2
公开(公告)日：2011-06-07
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/76
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件。 在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。 半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。 检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。 从确定的位置确定半导体衬底的x-y空间取向。 考虑了其他方面和实现。
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8.发明申请Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件公开(公告)号：US20070269994A1
公开(公告)日：2007-11-22
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。 在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。 半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。 检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。 从确定的位置确定半导体衬底的x-y空间取向。 考虑了其他方面和实现。
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9.发明申请Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices 有权确定包含集成电路的半导体衬底的X-Y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件公开(公告)号：US20110204526A1
公开(公告)日：2011-08-25
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/48
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。 在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。 半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。 检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。 从确定的位置确定半导体衬底的x-y空间取向。 考虑了其他方面和实现。
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公开(公告)号：US20100059898A1
公开(公告)日：2010-03-11
申请号：US12209052
申请日：2008-09-11
申请人： Brent Keeth , Mark Hiatt , Terry R. Lee , Mark Tuttle , Rahul Advani , John F. Schreck
发明人： Brent Keeth , Mark Hiatt , Terry R. Lee , Mark Tuttle , Rahul Advani , John F. Schreck
CPC分类号： H01L25/0657 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L25/0655 , H01L2223/6677 , H01L2224/0401 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2924/01004 , H01L2924/15311 , Y10T29/49165
摘要： Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
摘要翻译： 一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯，第二管芯和第二管芯， 被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。
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