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公开(公告)号：US4364620A
公开(公告)日：1982-12-21
申请号：US261236
申请日：1980-09-05
CPC分类号： H05K7/023
摘要： A socket (10) is described for housing similar integrated circuits (#1, #2). The socket (10) comprises a center support (14) which includes integral end panels (14a, 14b). The center support further includes a plurality of upstanding separators (42, 44) which form a plurality of recesses (46, 48). Side panels (18, 20) are joined to the center support to form first and second chambers (23, 24). A bottom plate (16) is connected to the center support (14) and side panels (18, 20). A lead frame (22) is positioned within the first and second chambers to provide metallic strips within the recesses (46, 48). In certain of the recesses the metallic strips extend from corresponding recesses in the two chambers (23, 24) and connect to a respective socket lead (12). In other selected recesses a metallic strip extends directly to connect to a package lead (12) such that there is no direct connection between common recesses. The integrated circuits (#1, #2) are positioned within the chambers (23, 24) such that the leads of the integrated circuits (#1, #2) are received within the recesses (46, 48). Certain leads of the devices (#1, #2) are connected in common to a socket lead (12) while other leads of the devices (#1, #2) are connected independently to socket leads (12) such that the two devices (#1, #2) can be operated independently.
摘要翻译： PCT No.PCT / US80 / 01139 Sec。 371日期1980年9月5日 102（e）1980年9月5日PCT申请1980年9月5日PCT公布。 出版物WO82 / 00923 日期为1982年3月18日。描述了一种用于容纳类似集成电路（＃1，＃2）的插座（10）。 插座（10）包括中心支撑件（14），其包括一体式端板（14a，14b）。 中心支撑件还包括形成多个凹部（46,48）的多个直立分离器（42,44）。 侧板（18,20）连接到中心支撑件以形成第一和第二腔室（23,24）。 底板（16）连接到中心支撑件（14）和侧板（18,20）。 引线框架（22）定位在第一和第二腔室内以在凹槽（46,48）内提供金属条。 在某些凹槽中，金属条从两个腔室（23,24）中的相应凹部延伸并连接到相应的插座引线（12）。 在其他选定的凹槽中，金属条直接延伸以连接到封装引线（12），使得在公共凹槽之间不存在直接连接。 集成电路（＃1，＃2）位于室（23,24）内，使得集成电路（＃1，＃2）的引线被容纳在凹部（46,48）内。 器件（＃1，＃2）的某些引线共同连接到插座引线（12），而器件（＃1，＃2）的其他引线独立地连接到插座引线（12），使得两个器件 （＃1，＃2）可以独立运行。
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公开(公告)号：US08129957B2
公开(公告)日：2012-03-06
申请号：US12077597
申请日：2008-03-19
申请人： Robert J. Martin
发明人： Robert J. Martin
CPC分类号： H02P9/305 , H02P29/032
摘要： An alternator system includes a field circuit, a regulator that regulates a field circuit electrical flow through the field circuit, and an output current sensor that detects an actual current output from the alternator system. The alternator system further includes a controller that communicates with the regulator to vary the field circuit electrical flow based on the actual current detected by the output current sensor.
摘要翻译： 交流发电机系统包括励磁电路，调节通过励磁电路的励磁电路电流的调节器以及检测来自交流发电机系统的实际电流输出的输出电流传感器。 交流发电机系统还包括控制器，其与调节器通信，以基于由输出电流传感器检测到的实际电流改变励磁电路电流。
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公开(公告)号：US07942958B1
公开(公告)日：2011-05-17
申请号：US09120664
申请日：1998-07-22
IPC分类号： C09D5/16
CPC分类号： C07D213/89 , A01N25/26 , A01N59/16 , A61K8/11 , A61K8/4933 , A61K31/00 , A61K2800/412 , A61K2800/56 , A61Q5/006 , A61Q17/005 , A61Q19/10 , C09D5/1612 , A01N43/40 , A01N59/20 , A01N2300/00
摘要： A biocidal composition is disclosed comprising composite particles, each of the composite particles containing a shell and a core, the core comprising a metal or a metal-containing compound wherein the metal is a moiety selected from the group consisting of zinc, copper, bismuth, silver, zirconium, and combinations thereof, the shell comprising a pyrithione adduct comprising the reaction product of pyrithione with a portion of the core metal or metal compound. In one aspect, an anti-fouling composition is disclosed comprising (a) an anti-soft-fouling effective amount of copper pyrithione; and (b) an anti-hard-fouling effective amount of a copper-containing salt, or oxide or hydroxide thereof. The present invention also relates to a method of making an antifouling composition comprising particles of copper pyrithione and a copper-containing salt that is effective against hard-fouling and soft-fouling organisms.
摘要翻译： 公开了一种杀生物组合物，其包含复合颗粒，每个复合颗粒含有壳和芯，所述芯包含金属或含金属的化合物，其中所述金属是选自锌，铜，铋， 银，锆及其组合，壳包含吡啶硫酮加合物，其包含吡啶硫酮与一部分核心金属或金属化合物的反应产物。 一方面，公开了一种防污组合物，其包含（a）抗软污染有效量的吡啶硫酮铜; 和（b）抗结垢有效量的含铜盐，或其氧化物或氢氧化物。 本发明还涉及一种制备防污组合物的方法，所述防污组合物包含对抗硬污垢和软污染生物有效的吡啶硫酮铜颗粒和含铜盐。
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公开(公告)号：US20090237037A1
公开(公告)日：2009-09-24
申请号：US12077597
申请日：2008-03-19
申请人： Robert J. Martin
发明人： Robert J. Martin
IPC分类号： H02P9/14
CPC分类号： H02P9/305 , H02P29/032
摘要： An alternator system includes a field circuit, a regulator that regulates a field circuit electrical flow through the field circuit, and an output current sensor that detects an actual current output from the alternator system. The alternator system further includes a controller that communicates with the regulator to vary the field circuit electrical flow based on the actual current detected by the output current sensor.
摘要翻译： 交流发电机系统包括励磁电路，调节通过励磁电路的励磁电路电流的调节器以及检测来自交流发电机系统的实际电流输出的输出电流传感器。 交流发电机系统还包括控制器，其与调节器通信，以基于由输出电流传感器检测到的实际电流改变励磁电路电流。
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5.发明申请公开(公告)号：US20080184188A1
公开(公告)日：2008-07-31
申请号：US11669202
申请日：2007-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.
摘要翻译： 一种用于产生掩模数据的方法包括：接收一组路由定义，使得能够使用具有相同小区间距的导体路由方案，响应于该组的特征识别位置，呈现掩模数据的一部分的表示并应用选择成员 的路由定义集合来定位和定义在掩模数据中建模的导体。 设计工具包括内存和处理器。 存储器存储使得具有相同单元间距的导体路由方案的路由定义。 处理器从路由定义集合接收标识选择路由定义的输入。 处理器执行逻辑，其产生响应于路由定义的特性的点阵列。 处理器还执行配置成限制集成电路中导体的相对位置和宽度的逻辑。
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公开(公告)号：US07213862B1
公开(公告)日：2007-05-08
申请号：US11175481
申请日：2005-07-07
申请人： Robert J. Martin
发明人： Robert J. Martin
IPC分类号： B60N2/08
CPC分类号： B60R25/014
摘要： A locking assembly includes a first housing including legs at opposed corners and including a flange extending from a bottom thereof that includes an aperture for receiving a fastener therethrough. The first housing has a pair of slots formed along the top thereof, a third slot medially formed of the pair of slots, defines a cavity therein and has a notch in a rear thereof. A second housing is positional within the first housing and includes a conduit that has a threaded inner surface and guide tracks conjoined to the sidewalls thereof. A mechanism is included for adapting the second housing between retracted and extended positions. A mechanism is included for prohibiting the seat from unintentionally biasing between retracted and extended positions. An actuating arm having is disposed within the third slot, is pivotally connected to the first housing and includes a spring member.
摘要翻译： 锁定组件包括第一壳体，该第一壳体包括在相对的拐角处的腿，并且包括从底部延伸的凸缘，该凸缘包括用于接收穿过其中的紧固件的孔。 第一壳体具有沿其顶部形成的一对槽，由一对槽中间地形成的第三槽，在其中限定空腔，并且在其后部具有凹口。 第二壳体位于第一壳体内并且包括具有螺纹内表面和与其侧壁结合的导轨的导管。 包括用于使第二壳体在缩回位置和伸出位置之间适配的机构。 包括用于禁止座椅在收缩位置和伸出位置之间无意偏压的机构。 具有设置在第三槽内的致动臂枢转地连接到第一壳体并且包括弹簧构件。
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公开(公告)号：US06657195B1
公开(公告)日：2003-12-02
申请号：US09665959
申请日：2000-09-21
IPC分类号： H01L3109
CPC分类号： B82Y20/00 , G01J3/42 , H01L27/14652 , H01L31/035236
摘要： A quantum well infrared photodetector focal plane array is disclosed wherein each detector structure of the array comprises two vertically stacked quantum well layers. Each of the quantum well layers are individually biased by separate bias voltages and the separate bias voltages are modulated to produce two or more measurements at different spectral bands. Each detector structure of the array can therefore perform measurements of incident infrared energy in at least four separate spectral bands. This technique of measuring incident infrared energy in four separate spectral bands can advantageously be applied to the discrimination of hot gas sources from background infrared clutter.
摘要翻译： 公开了一种量子阱红外光电探测器焦平面阵列，其中阵列的每个检测器结构包括两个垂直堆叠的量子阱层。 每个量子阱层被单独的偏置电压单独地偏置，并且单独的偏置电压被调制以在不同的光谱带处产生两个或更多个测量。 因此，阵列的每个检测器结构可以在至少四个分离的光谱带中执行入射的红外能量的测量。 这种在四个独立光谱带中测量入射红外能量的技术可以有利地应用于从背景红外杂波区分热气源。
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8.发明授权Interlocking and insulated form pattern assembly for creating a wall structure for receiving poured concrete 失效联锁和绝缘形式图案组合，用于创建用于接收倾倒的混凝土的墙体结构
公开(公告)号：US5839243A
公开(公告)日：1998-11-24
申请号：US713522
申请日：1996-09-13
申请人： Robert J. Martin
发明人： Robert J. Martin
CPC分类号： E04C1/40 , E04B2/8629 , E04B2002/0217 , E04B2002/867 , E04B2002/8676
摘要： An interlocking and insulated form pattern assembly for creating a wall construction for receiving a poured concrete. A plurality of form structures each are constructed in a substantially rectangular fashion with a height, length and width and include pluralities of arcuately shaped inner walls which define both vertically and longitudinally extending concrete filling passageways. The forms are interlockingly arranged according to a desired stacking arrangement so that the vertically and longitudinally filling passageways extending continuously throughout the erected wall structure. Moisture drainage channels likewise extend in interconnected fashion both horizontally and vertically within the form structures and are arranged in alignment with identical channels in succeeding form structures to provide internal drainage capabilities to the form assembly.
摘要翻译： 一种互锁和绝缘的形式图案组件，用于产生用于接收浇注的混凝土的墙壁结构。 多个形式结构各自以高度，长度和宽度的大致矩形的方式构造，并且包括限定垂直和纵向延伸的混凝土填充通道的多个弧形内壁。 这些形式根据期望的堆叠布置互锁地布置，使得垂直和纵向填充通道连续延伸穿过竖立的墙壁结构。 湿气排放通道同样在水平和垂直方向上以互连的方式延伸，并且在后续形式的结构中与相同的通道对准地设置，以向模板组件提供内部排水能力。
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公开(公告)号：US5566382A
公开(公告)日：1996-10-15
申请号：US570279
申请日：1995-12-11
CPC分类号： G02B26/08 , G01S13/9005
摘要： A SAR radar has an optical processor which uses an electrical-signal-to-light modulator. The modulator includes a tapped delay line which may be either analog or digital, and the signals tapped from the delay line are applied to an array of temporary storage elements, which in the case of analog signals may be a capacitive sample-and-hold, or for digital signals may include storage registers. In order to improve the signal-to-noise ratio (SNR) by comparison with a processor using an acoustic modulator, the signals tapped from the delay line are sampled at a display sampling rate, which is very low by comparison with the signal sampling rate or the highest frequency of interest, and the sampled signals are held until the next following display rate pulse. The signals held in the temporary storage elements are applied to the modulator elements, so that the optical pattern remains fixed for relatively long periods of time during which the optical processing can integrate photons for improved SNR.
摘要翻译： SAR雷达具有使用电信号到光调制器的光学处理器。 调制器包括可以是模拟或数字的抽头延迟线，并且从延迟线抽头的信号被施加到临时存储元件阵列，在模拟信号的情况下可以是电容采样保持， 或者对于数字信号可以包括存储寄存器。 为了通过与使用声学调制器的处理器进行比较来提高信噪比（SNR），从延迟线抽头的信号以显示采样率进行采样，其显示采样率与信号采样率相比非常低 或感兴趣的最高频率，并且保持采样信号直到下一个跟随显示速率脉冲。 保存在临时存储元件中的信号被施加到调制器元件，使得光学图案保持固定相对较长的时间段，在该时间期间光学处理可以集成光子以改善SNR。
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10.发明授权
公开(公告)号：US5329176A
公开(公告)日：1994-07-12
申请号：US137902
申请日：1993-09-29
IPC分类号： G06F7/50 , G06F7/501 , H03K19/094 , H03K19/096 , H03K19/21 , H03K19/017
CPC分类号： G06F7/5016 , H03K19/094 , H03K19/0966 , H03K19/215
摘要： A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.
摘要翻译： 为具有级联自定时动态逻辑门的逻辑块提供时钟系统和方法。 动态逻辑门并行预充电，并对矢量输入进行自定时逻辑评估，以得出矢量输出。 评估完成检测器监视逻辑块的输出，并确定矢量输出何时有效。 边缘检测器检测任意周期性定时信号的上升沿和下降沿。 最后，由边缘检测器设置逻辑块时钟发生器并由评估完成检测器复位，以便向逻辑块提供预充电信号，从而定义相应的预充电周期，并且提供用于自适应逻辑评估的评估周期 逻辑块。 在具体实现中，逻辑评估的速度是系统时钟速度的两倍。
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