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106 条记录 (耗时 0.024 秒)

    Verification algorithm for metal-oxide resistive memory
    1.
    发明授权
    Verification algorithm for metal-oxide resistive memory 有权
    金属氧化物电阻记忆体验证算法

    公开(公告)号：US08699258B2

    公开(公告)日：2014-04-15

    申请号：US13212493

    申请日：2011-08-18

    申请人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    发明人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C7/1045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

    摘要翻译： 描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。 本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。 在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

    VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY
    2.
    发明申请
    VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY 有权
    用于金属氧化物电阻记忆的验证算法

    公开(公告)号：US20120188813A1

    公开(公告)日：2012-07-26

    申请号：US13212493

    申请日：2011-08-18

    申请人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    发明人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    IPC分类号： G11C11/21

    CPC分类号： G11C7/1045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

    摘要翻译： 描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。 本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。 在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

    THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS
    4.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS 有权
    三维尺寸记忆阵列

    公开(公告)号：US20130153846A1

    公开(公告)日：2013-06-20

    申请号：US13330525

    申请日：2011-12-19

    申请人： Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    发明人： Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    IPC分类号： H01L45/00 ,  H01L21/8239

    CPC分类号： H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

    摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

    摘要翻译： 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

    Three dimensional memory array adjacent to trench sidewalls
    5.
    发明授权
    Three dimensional memory array adjacent to trench sidewalls 有权
    与沟槽侧壁相邻的三维存储器阵列

    公开(公告)号：US09035275B2

    公开(公告)日：2015-05-19

    申请号：US13330525

    申请日：2011-12-19

    申请人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    发明人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    IPC分类号： H01L29/06 ,  H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

    摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

    摘要翻译： 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

    Resistance memory cell and operation method thereof
    6.
    发明授权
    Resistance memory cell and operation method thereof 有权
    电阻记忆单元及其操作方法

    公开(公告)号：US09070860B2

    公开(公告)日：2015-06-30

    申请号：US13601209

    申请日：2012-08-31

    申请人： Wei-Chih Chien ,  Ming-Hsiu Lee

    发明人： Wei-Chih Chien ,  Ming-Hsiu Lee

    IPC分类号： H01L45/00 ,  G11C13/00 ,  G11C29/50

    CPC分类号： H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2213/72 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/146

    摘要： A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

    摘要翻译： 提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。 钨金属层设置在第一电极上。 金属氧化物层设置在钨金属层上。 第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。 桥接部分设置在金属氧化物层上或围绕金属氧化物层。 电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

    Three-dimensional array structure for memory devices
    8.
    发明授权
    Three-dimensional array structure for memory devices 有权
    用于存储器件的三维阵列结构

    公开(公告)号：US08937291B2

    公开(公告)日：2015-01-20

    申请号：US13528754

    申请日：2012-06-20

    申请人： Ming-Hsiu Lee ,  Wei-Chih Chien

    发明人： Ming-Hsiu Lee ,  Wei-Chih Chien

    IPC分类号： H01L47/00 ,  H01L29/06

    CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/1022

    摘要： A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

    摘要翻译： 所公开的存储器件包括三维阵列结构，其包括设置在存储层之间的存储层和晶体管结构。 每个存储器层连接到公共电极，并且每个晶体管结构包括共享公共列结构和公共基极结构的晶体管。 晶体管还各自包括通过公共基底结构与公共柱结构间隔开的连接器结构。

    MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE
    10.
    发明申请
    MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
    通过改变复位电压，PCM的多级电容编程

    公开(公告)号：US20110069538A1

    公开(公告)日：2011-03-24

    申请号：US12564904

    申请日：2009-09-22

    申请人： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

    发明人： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

    摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.

    摘要翻译： 相变存储器件及其编程方法。 该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。 该方法包括确定用于相变存储器件的特征化的RESET电流斜率。 该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。 该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。 如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。 在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。