公开(公告)号：US4808273A

公开(公告)日：1989-02-28

申请号：US192343

申请日：1988-05-10

申请人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

发明人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

IPC分类号： H01L21/74 ,  H01L21/768 ,  C25D5/02

CPC分类号： H01L21/76898

摘要： A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.

摘要翻译： 公开了一种用于在半导体晶片中形成完全金属化的通孔的方法。 金属焊盘与导电互连网络一起形成在半导体晶片的一个面上。 然后沉积绝缘层以覆盖晶片的这个面。 孔在晶片的相对表面被蚀刻，直至并暴露出金属焊盘的一部分。 然后使用金属垫作为阴极，通过电镀将通孔用金属完全填充。

公开(公告)号：US4978639A

公开(公告)日：1990-12-18

申请号：US295300

申请日：1989-01-10

申请人： Chang-Hwang Hua ,  Simon S. Chan ,  Ding-Yuan S. Day ,  Adrian C. Lee

发明人： Chang-Hwang Hua ,  Simon S. Chan ,  Ding-Yuan S. Day ,  Adrian C. Lee

IPC分类号： H01L21/288 ,  H01L21/768

CPC分类号： H01L21/78 ,  H01L21/288 ,  H01L21/76898 ,  Y10S148/028 ,  Y10S148/135 ,  Y10S438/977

摘要： Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.

摘要翻译： 在半导体芯片上同时形成金属化的通孔和环绕的金属电镀，方法是在晶片的前表面上形成光致抗蚀剂掩模以在金属焊盘上打开窗口以及需要环绕电镀的栅格区域; 如果需要则蚀刻暴露的金属，并通过反应离子蚀刻在晶片中形成通孔和沟槽，其深度小于晶片的总厚度; 通过化学镀方法沿沟槽和通孔的壁沉积薄导电膜; 通过电解方法用导电金属电镀槽和通孔; 与两个槽和通孔的地板一起去除晶片的背面（“后退”），以露出通孔壁上的金属并分离各个芯片; 并且在各个芯片的背面上沉积导电金属，以完成接地路径。

公开(公告)号：US4842699A

公开(公告)日：1989-06-27

申请号：US192199

申请日：1988-05-10

申请人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

发明人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

IPC分类号： C25D5/02 ,  H01L21/768 ,  H01L23/48

CPC分类号： C25D5/022 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002

摘要： A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.

摘要翻译： 一种使用金属掩模同时选择性地电镀与半导体晶片相关的通孔和散热器的方法，包括以下步骤：（a）用绝缘层涂覆晶片的第一侧以防止在该第一侧上的电镀; （b）在晶片的与第一侧相对的第二面上图案化，用于限定不应发生电镀的区域的金属掩模; （c）通过所述晶片形成通孔; （d）沉积薄的导电膜以覆盖通孔的底部和壁以及未被金属掩模覆盖的晶片的第二面的区域; 和（e）如果需要的话，对所得的晶片进行电解电镀，同时超声波地搅动电解质，以确保足够的电解质输送到通孔中用于均匀的电镀。

公开(公告)号：US5288660A

公开(公告)日：1994-02-22

申请号：US11998

申请日：1993-02-01

申请人： Chang-Hwang Hua ,  Simon S. Chan ,  Ding-Yuan Day

发明人： Chang-Hwang Hua ,  Simon S. Chan ,  Ding-Yuan Day

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/283 ,  H01L21/312

CPC分类号： H01L21/76802 ,  H01L21/0274

摘要： A T-shaped electrode is formed on a semiconductor substrate by first forming a dielectric film on the substrate. A first layer of photoresist is applied on the upper surface of the dielectric film, and a second layer of photoresist is applied over the first layer of photoresist. The first and second layers of photoresist have different optical properties, requiring different wavelengths of ultraviolet for exposure before developing. Portions of the first and second photoresist layers and the dielectric film are selectively removed by photolithographic techniques with one masking step for forming an opening to the substrate. The first and second photoresist layers adjacent to the opening are ion etched to expose the upper surface of the dielectric film adjacent to the opening. A portion of the first photoresist layer adjacent to the opening is removed to undercut the second photoresist layer. Metal is deposited in the opening and on the exposed upper surface of the dielectric film to form a T-shaped electrode. The first and second photoresist layers are then removed, thereby also removing metal deposited on top of the second layer of photoresist.

摘要翻译： 首先在基板上形成电介质膜，在半导体基板上形成T字形电极。 在电介质膜的上表面上施加第一层光致抗蚀剂，在第一层光致抗蚀剂上施加第二层光致抗蚀剂。 第一层和第二层光致抗蚀剂具有不同的光学性质，在显影之前需要不同波长的紫外线进行曝光。 通过光刻技术选择性地去除第一和第二光致抗蚀剂层和电介质膜的部分，其中一个掩模步骤用于形成对该基底的开口。 邻近开口的第一和第二光致抗蚀剂层被离子蚀刻以暴露与开口相邻的电介质膜的上表面。 去除与开口相邻的第一光致抗蚀剂层的一部分以切割第二光致抗蚀剂层。 金属沉积在介质膜的开口和暴露的上表面上以形成T形电极。 然后去除第一和第二光致抗蚀剂层，从而也去除沉积在第二层光致抗蚀剂上的金属。

公开(公告)号：US08314454B2

公开(公告)日：2012-11-20

申请号：US12970687

申请日：2010-12-16

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

公开(公告)号：US07144818B2

公开(公告)日：2006-12-05

申请号：US10729479

申请日：2003-12-05

申请人： Mario M. Pelella ,  Simon S. Chan

发明人： Mario M. Pelella ,  Simon S. Chan

IPC分类号： H01L21/311

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US06291339B1

公开(公告)日：2001-09-18

申请号：US09225218

申请日：1999-01-04

申请人： Steven C. Avanzino ,  Simon S. Chan

发明人： Steven C. Avanzino ,  Simon S. Chan

IPC分类号： H01L214263

CPC分类号： H01L21/76819

摘要： A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

摘要翻译： 具有旋转低k间隙填充层的双层层间电介质用较高的k电介质层封装。 在封盖之前，由于图案密度对纺丝低k电介质层的厚度的影响，使旋转低k电介质层平坦化以减少或消除层的相对厚度的系统变化。 通过去除低k电介质层和覆盖层的相对厚度的变化，均匀厚的复合层间电介质的有效介电常数与电路上的位置无关，防止电路速度的差异和时钟偏差的产生 电路。

公开(公告)号：US6093635A

公开(公告)日：2000-07-25

申请号：US993124

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

发明人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。 在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

公开(公告)号：US07879718B2

公开(公告)日：2011-02-01

申请号：US11616544

申请日：2006-12-27

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L21/44

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

摘要翻译： 提供一种用于在半导体存储器件中形成互连的方法。 该方法包括在衬底上形成一对源极选择晶体管。 源区域形成在一对源极选择晶体管之间的衬底中。 在所述一对源极选择晶体管之间形成第一层间电介质。 掩模层沉积在一对源极选择晶体管和层间电介质上，其中掩模层限定了一对源极选择晶体管之间的局部互连区域，其宽度小于一对源选择晶体管之间的距离。 蚀刻半导体存储器件以去除局部互连区域中的第一层间电介质的一部分，从而暴露源极区域。 在局部互连区域中形成金属接触。

公开(公告)号：US07538383B1

公开(公告)日：2009-05-26

申请号：US11416703

申请日：2006-05-03

申请人： Meng Ding ,  Simon S. Chan

发明人： Meng Ding ,  Simon S. Chan

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568

摘要： According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.

摘要翻译： 根据一个示例性实施例，两比特存储器单元包括位于衬底上方的栅极堆叠，其中栅极堆叠包括电荷捕获层。 电荷捕获层包括第一和第二导电段和氮化物区段，其中氮化物区段位于第一和第二导电区段之间。 氮化物区段将第一导电段与第二导电段电绝缘。 第一和第二导电段在双位存储单元中提供相应的第一和第二数据位存储单元。 栅极堆叠还可以包括位于衬底和电荷俘获层之间的较低氧化物段。 栅极堆叠还可以包括位于电荷捕获层上方的上部氧化物段。 栅极堆叠可以位于第一介电段和第二介电段之间，其中第一和第二介电段位于相应的第一和第二位线之上。