公开(公告)号：US07068107B2

公开(公告)日：2006-06-27

申请号：US10805297

申请日：2004-03-22

申请人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai

IPC分类号： H03F3/30

CPC分类号： H03G1/0088

摘要： The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

摘要翻译： 本发明的可变增益放大器至少包括一个运算放大器。 通过选择输出级之一，根据需要选择反馈电阻，并根据所选反馈电阻的电阻决定可变增益放大器的增益。 通过调整可变增益放大器的增益，接收信号可以根据设计要求进行放大或衰减。 可变增益放大器可以包括两级架构，其中第一级用于粗增益调整，第二级用于精细增益调整。 两级可变增益放大器的增益可以很容易地调整到所需的值。

公开(公告)号：US07138869B2

公开(公告)日：2006-11-21

申请号：US10748667

申请日：2003-12-31

申请人： Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai ,  Wen-Chi Wang

发明人： Chao-Cheng Lee ,  Jui-Cheng Huang ,  Jui-Yuan Tsai ,  Wen-Chi Wang

IPC分类号： H03G3/12

CPC分类号： H03H11/126 ,  H03H7/24

摘要： An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

摘要翻译： 具有高时间常数的放大器电路。 运算放大器包括耦合到地的非转换输入端，转换输入端和输出端。 包括至少一个级的第一电阻网络耦合在转换输入端和输出端之间。 第一电阻网络的每个级包括连接到第一节点的第一节点，第一电流路径和第二电流路径。 第一电阻网络的每个级的第一电流路径连接到下一级的第一节点，第一电阻网络的每一级的第二电流路径接地，并且第一电阻网络的第一级的第一电流路径 电阻网络连接到转换输入端。 加载单元耦合在转换输入端和输出端之间。

公开(公告)号：US20050225470A1

公开(公告)日：2005-10-13

申请号：US10907618

申请日：2005-04-08

申请人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

发明人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

IPC分类号： H03M1/14 ,  H03M1/10 ,  H03M1/12 ,  H03M1/38

CPC分类号： H03M1/1038 ,  H03M1/145

摘要： A pipeline ADC for converting an analog input signal to a digital output signal includes: a plurality of analog-to-digital converting units cascading in series to form a pipeline including a plurality of digital output ends; a calculation unit coupled to the analog-to-digital converting units for generating a plurality of calibration parameters in a first mode according to signals at the digital output ends; and a calibration unit coupled to the calculation unit and the analog-to-digital converting units for calibrating signals at the digital output ends in a second mode according to the calibration parameters, so as to generate the digital output signal.

摘要翻译： 用于将模拟输入信号转换为数字输出信号的流水线ADC包括：串联级联的多个模数转换单元，以形成包括多个数字输出端的流水线; 耦合到模数转换单元的计算单元，用于根据数字输出端的信号在第一模式中产生多个校准参数; 以及耦合到所述计算单元和所述模数转换单元的校准单元，用于根据所述校准参数以第二模式校准所述数字输出端的信号，以产生所述数字输出信号。

公开(公告)号：US20070030037A1

公开(公告)日：2007-02-08

申请号：US11459364

申请日：2006-07-24

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  G11C27/026

摘要： A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

摘要翻译： 参考电压产生电路包括具有第一端和第二端的第一电容器; 具有第三端和第四端的第二电容器; 用于选择性地将预定电压耦合到第一电容器的第一端的第一开关; 第二开关，用于选择性地将第二电容器的第三端耦合到第一电容器的第一端; 用于选择性地将第一电容器的第一端耦合到参考电压电平的第三开关; 以及用于选择性地将第一电容器的第二端耦合到参考电压电平的第四开关; 其中所述第一电容器在第一级中对所述预定电压进行采样，并在第二级中将电荷重新分配给所述第二电容器。

公开(公告)号：US20060044015A1

公开(公告)日：2006-03-02

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US07456769B2

公开(公告)日：2008-11-25

申请号：US11459364

申请日：2006-07-24

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M3/00

CPC分类号： G11C27/024 ,  G11C27/026

摘要： A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

摘要翻译： 参考电压产生电路包括具有第一端和第二端的第一电容器; 具有第三端和第四端的第二电容器; 用于选择性地将预定电压耦合到第一电容器的第一端的第一开关; 第二开关，用于选择性地将第二电容器的第三端耦合到第一电容器的第一端; 用于选择性地将第一电容器的第一端耦合到参考电压电平的第三开关; 以及用于选择性地将第一电容器的第二端耦合到参考电压电平的第四开关; 其中所述第一电容器在第一级中对所述预定电压进行采样，并且在第二级中将电荷重新分配给所述第二电容器。

公开(公告)号：US20050225462A1

公开(公告)日：2005-10-13

申请号：US10907673

申请日：2005-04-12

申请人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

发明人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/44

CPC分类号： H03M1/1038 ,  H03M1/44

摘要： A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

摘要翻译： 流水线ADC具有串联级联的多个模数转换单元以形成流水线。 用于流水线ADC的纠错方法包括在第一模式期间，利用额外的模数转换模块来测量多个模数转换单元; 在所述测量步骤中根据所述额外模数转换模块的数字输出值计算多个校正常数组; 并且在第二模式期间，根据校正常数组来校正多个模数转换单元的输出信号。

公开(公告)号：US07279931B2

公开(公告)日：2007-10-09

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US07253764B2

公开(公告)日：2007-08-07

申请号：US11463014

申请日：2006-08-08

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/502 ,  H03M1/66 ,  H03M3/464

摘要： A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

摘要翻译： 参考电压产生电路包括：第一电容器; 第二电容器; 参考电压采样电容器; 用于交替地将第二电容器耦合到预定电压以允许第二电容器对预定电压进行采样的第一开关; 用于将第二电容器交替地耦合到第一电容器的第二开关，以允许第二电容器与第一电容器重新分配电荷，以便产生参考电压; 以及第三开关，用于将第一电容器交替地耦合到参考电压采样电容器，以允许参考电压采样电容器与第一电容器重新分配电荷，以便输出参考电压。

公开(公告)号：US20070046523A1

公开(公告)日：2007-03-01

申请号：US11463014

申请日：2006-08-08

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/502 ,  H03M1/66 ,  H03M3/464

摘要： A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

摘要翻译： 参考电压产生电路包括：第一电容器; 第二电容器; 参考电压采样电容器; 用于交替地将第二电容器耦合到预定电压以允许第二电容器对预定电压进行采样的第一开关; 用于将第二电容器交替地耦合到第一电容器的第二开关，以允许第二电容器与第一电容器重新分配电荷，以便产生参考电压; 以及第三开关，用于将第一电容器交替地耦合到参考电压采样电容器，以允许参考电压采样电容器与第一电容器重新分配电荷，以便输出参考电压。