公开(公告)号：US20120188449A1

公开(公告)日：2012-07-26

申请号：US13103109

申请日：2011-05-09

申请人： Wen-Yi Chen ,  Jau-Yih Lin ,  Pang-Chih Liu

发明人： Wen-Yi Chen ,  Jau-Yih Lin ,  Pang-Chih Liu

IPC分类号： H04N5/10

CPC分类号： H04N5/06

摘要： Vertical sync signal separation apparatus and method are provided. The vertical sync signal separation apparatus includes a parameter detecting unit, a threshold generating unit and a vertical sync signal generating unit. The parameter detecting unit measures a composite sync signal to obtain a maximum and a second maximum positive pulse width, and a maximum and a second maximum negative pulse width. The threshold generating unit outputs a positive pulse threshold based on the maximum and second maximum positive pulse width, and outputs a negative pulse threshold based on the maximum and second maximum negative pulse width. The vertical sync signal generating unit outputs a vertical sync signal by comparing the composite sync signal against the positive pulse threshold and the negative pulse threshold. As such, this apparatus can correctly separate a vertical sync signal from composite sync signals with different standards, thus increasing its supportability.

摘要翻译： 提供垂直同步信号分离装置和方法。 垂直同步信号分离装置包括参数检测单元，阈值生成单元和垂直同步信号生成单元。 参数检测单元测量复合同步信号以获得最大和第二最大正脉冲宽度以及最大和第二最大负脉冲宽度。 阈值生成单元基于最大和第二最大正脉冲宽度输出正脉冲阈值，并且基于最大和第二最大负脉冲宽度输出负脉冲阈值。 垂直同步信号产生单元通过将复合同步信号与正脉冲阈值和负脉冲阈值进行比较来输出垂直同步信号。 因此，该装置可以从不同标准的复合同步信号中正确地分离垂直同步信号，从而增加其可支持性。

公开(公告)号：US20140252552A1

公开(公告)日：2014-09-11

申请号：US13789340

申请日：2013-03-07

申请人： Chai Ean Gill ,  Wen-Yi Chen

发明人： Chai Ean Gill ,  Wen-Yi Chen

IPC分类号： H01L27/02 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L27/0251 ,  H01L27/1203

摘要： Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

摘要翻译： 提供了电子器件封装的芯片结构和相关的制造方法。 示例性管芯结构包括具有包括形成在其上的半导体器件的半导体材料的第一层，半导体材料的手柄层以及处理层和第一层之间的介电材料掩埋层的衬底。 模具结构还包括在第一半导体材料层中的多个分流区域，其中每个分流区域包括电连接到半导体材料的手柄层的第一层中的掺杂区域和掺杂区域下面的体区域 其与半导体器件下面的第一层的至少一部分相邻。

公开(公告)号：US20100315754A1

公开(公告)日：2010-12-16

申请号：US12625449

申请日：2009-11-24

申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H02H1/0007

摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

摘要翻译： 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。 晶体管与电容器耦合，检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此，形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。

公开(公告)号：US20070230073A1

公开(公告)日：2007-10-04

申请号：US11428571

申请日：2006-07-05

申请人： Ming-Dou Ker ,  Wen-Yi Chen

发明人： Ming-Dou Ker ,  Wen-Yi Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.

摘要翻译： 提出了一种高耐压电源轨ESD钳位电路，其中电路器件可以在没有栅极氧化可靠性问题的工艺限制的三倍大的高电源电压下安全工作。 此外，ESD检测电路用于通过基板触发技术有效地提高整个ESD保护功能。 由于仅使用低电压（1 * VDD）器件来实现高电压（3 * VDD）公差的目标，所以提出的设计为具有混合电压接口的芯片提供了具有成本效益的电源轨ESD保护解决方案。

公开(公告)号：US09502890B2

公开(公告)日：2016-11-22

申请号：US13900226

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/66 ,  H01L27/02 ,  H02H9/04 ,  H01L29/732

CPC分类号： H02H9/044 ,  H01L27/0259 ,  H01L29/7322 ,  H02H9/046

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.

摘要翻译： 提供了保护装置结构和相关制造方法。 一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域 具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域， 第二导电类型。 第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

公开(公告)号：US09129806B2

公开(公告)日：2015-09-08

申请号：US13900256

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/66 ,  H01L27/02

CPC分类号： H01L27/0259

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.

摘要翻译： 提供了保护装置结构和相关制造方法。 示例性的半导体保护装置包括具有第一导电类型的基极阱区域，在基极阱区域内的发射极区域具有与第一导电类型相反的第二导电类型，具有第二导电类型的集电极区域，具有第二导电类型的第一浮动区域， 在发射极区域和集电极区域之间的基极阱区域内的第二导电类型，以及在第一浮动区域和集电极区域之间的基极阱区域内具有第一导电类型的第二浮动区域。 基极区域内的浮动区域电连接以减小电流增益并改善保持电压。

公开(公告)号：US20140235465A1

公开(公告)日：2014-08-21

申请号：US13770987

申请日：2013-02-19

申请人： Wen-Yi Chen ,  Yun-Shyong Yang ,  Hardy Wai-Hong Chan

发明人： Wen-Yi Chen ,  Yun-Shyong Yang ,  Hardy Wai-Hong Chan

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6832 ,  C12Q2525/113 ,  C12Q2563/116

摘要： A method of using Neutrilized DNA (N-DNA) as a surface probe for a high throughput detection platform is disclosed. FET and SPRi are used as high throughput detection platforms to demonstrate that the N-DNA surface probe produces good results and enhances detection sensitivity. The N-DNA modifies the charged oxygen ions (O−) on the phosphate backbone through methylation, ethylation, propylation, or alkylation, so that the backbone is not charged after this modification to increase the hybridization efficiency, sensitivity and to make the signal more clear.

摘要翻译： 公开了一种使用中性DNA（N-DNA）作为高通量检测平台的表面探针的方法。 FET和SPRi用作高通量检测平台，以证明N-DNA表面探针产生良好的结果并增强检测灵敏度。 N-DNA通过甲基化，乙基化，丙基化或烷基化修饰磷酸酯骨架上的带电氧离子（O-），从而在此修饰后主链不带电以提高杂交效率，灵敏度，使信号更多 明确。

公开(公告)号：US20140218829A1

公开(公告)日：2014-08-07

申请号：US13759241

申请日：2013-02-05

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

摘要翻译： 提供集成电路。 集成电路可以包括但不限于第一节点，被配置为耦合到地的第二节点，输出驱动器和电耦合到第一节点，第二节点和输出驱动器的静电放电电路 。 静电放电电路可以包括但不限于被配置为检测第一节点处的静电放电事件的高通滤波器，电耦合到高通滤波器和输出驱动器的驱动级电路，驱动级电路配置 当所述高通滤波器检测到所述静电放电事件时，接收来自所述高通滤波器的信号，并且还被配置为响应于来自所述高通滤波器的信号将所述输出驱动器的输入分流到所述第二节点，并且 降压电路电耦合到驱动级电路并且被配置为偏置驱动级电路。

公开(公告)号：US09112351B2

公开(公告)日：2015-08-18

申请号：US13759241

申请日：2013-02-05

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

摘要翻译： 提供集成电路。 集成电路可以包括但不限于第一节点，被配置为耦合到地的第二节点，输出驱动器和电耦合到第一节点，第二节点和输出驱动器的静电放电电路 。 静电放电电路可以包括但不限于被配置为检测第一节点处的静电放电事件的高通滤波器，电耦合到高通滤波器和输出驱动器的驱动级电路，驱动级电路配置 当所述高通滤波器检测到所述静电放电事件时，接收来自所述高通滤波器的信号，并且还被配置为响应于来自所述高通滤波器的信号将所述输出驱动器的输入分流到所述第二节点，并且 降压电路电耦合到驱动级电路并且被配置为偏置驱动级电路。

公开(公告)号：US08258757B2

公开(公告)日：2012-09-04

申请号：US12785145

申请日：2010-05-21

申请人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

发明人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

IPC分类号： H01M10/44 ,  H01M10/46

CPC分类号： H02J7/0083

摘要： A charging method fit for use with and applicable to a rechargeable battery is provided. The charging method involves charging the rechargeable battery to a first preset voltage and then charging the rechargeable battery to a second preset voltage. The charging method includes the steps of: (a) using the first preset current as a charging current, and performing the constant current charging of the rechargeable battery by the first preset current until the rechargeable battery reaches the first preset voltage for the first instance; (b) subtracting a current difference value from the charging current used by the rechargeable battery to reach the first preset voltage in the preceding instance so as to obtain a new charging current, and performing the constant current charging of the rechargeable battery by the new charging current thus obtained until the rechargeable battery reaches the first preset voltage again; (c) repeating step (b) until the new charging current equals a second preset current; and step (d) using the second preset current of step (c) as another new charging current, and performing the constant current charging of the rechargeable battery by the second preset current until the rechargeable battery reaches a second preset voltage for the first instance.

摘要翻译： 提供适用于可充电电池的充电方法。 充电方法包括将可再充电电池充电到第一预设电压，然后将可再充电电池充电到第二预设电压。 充电方法包括以下步骤：（a）使用第一预置电流作为充电电流，并且通过第一预设电流执行可再充电电池的恒定电流充电直到可再充电电池首次达到第一预置电压; （b）从先前的例子中减去由可再充电电池使用的充电电流达到第一预设电压的电流差值，以获得新的充电电流，并通过新充电来执行可再充电电池的恒定电流充电 直到可再充电电池再次达到第一预置电压为止; （c）重复步骤（b），直到新的充电电流等于第二预设电流; 和步骤（d）使用步骤（c）的第二预设电流作为另一新的充电电流，并且通过第二预设电流执行可再充电电池的恒定电流充电，直到可再充电电池达到第一预定电压为止。