公开(公告)号：US20120241710A1

公开(公告)日：2012-09-27

申请号：US13052864

申请日：2011-03-21

申请人： Wenhu Liu ,  Kin-Leong Pey ,  Nagarajan Raghavan ,  Chee Mang Ng

发明人： Wenhu Liu ,  Kin-Leong Pey ,  Nagarajan Raghavan ,  Chee Mang Ng

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L45/1253 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

摘要： Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

摘要翻译： 通常，本文公开的主题涉及使用CMOS兼容过程制造RRAM单元。 公开了一种电阻随机存取存储器件，其包括半导体衬底，顶部电极，至少部分地形成在衬底中的至少一个金属硅化物底部电极，其中至少一部分底部电极位于顶部 以及位于所述顶部电极和所述至少一个底部电极的至少一部分之间的至少一个绝缘层。 公开了一种制造电阻随机存取存储器件的方法，其包括在半导体衬底中形成隔离结构从而限定封闭区域，执行至少一个离子注入工艺以在封闭区域内将掺杂剂原子注入到衬底中，在执行 所述至少一个离子注入工艺，在所述衬底的至少部分上方形成难熔金属层，以及执行至少一个热处理工艺，以在所述衬底中至少部分地形成至少一个金属硅化物底电极，其中至少一个 所述至少一个底部电极的一部分位于所述装置的顶部电极的至少一部分的下方。

公开(公告)号：US5956137A

公开(公告)日：1999-09-21

申请号：US186389

申请日：1998-11-05

申请人： Eng Hua Lim ,  Kin-Leong Pey ,  Harianto Wong ,  Kong Hean Lee

发明人： Eng Hua Lim ,  Kin-Leong Pey ,  Harianto Wong ,  Kong Hean Lee

IPC分类号： G01J3/44 ,  H01L21/00

CPC分类号： G01J3/44

摘要： An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.

摘要翻译： 描述了用于识别诸如细线图案的微结构中的相位的在线非破坏性方法。 这是通过观察微结构的拉曼光谱来实现的。 特别的应用是使用SALICIDE工艺制备的硅化物层，其中快速热退火之前和之后的晶相通常是不同的。 这反映在拉曼光谱中不同线的出现，从而可以确定每相的分数。 如果在退火期间硅化物层凝聚，则这也由拉曼光谱检测。 该方法已被成功地应用到约0.35微米的线宽。

公开(公告)号：US06180501B2

公开(公告)日：2001-01-30

申请号：US09418036

申请日：1999-10-14

申请人： Kin-Leong Pey ,  Chaw Sing Ho ,  Lap Chan

发明人： Kin-Leong Pey ,  Chaw Sing Ho ,  Lap Chan

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/28035 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66545

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种使硅化多晶硅栅极用于制造窄沟道CMOS器件时可能出现的局部机械应力问题最小化的方法。 本发明解决了避免多晶硅栅极中的典型的应力引起的问题，例如不均匀的硅化物（包括弯曲，变薄边缘等）和空隙，随着栅极长度的不断减小，这些问题变得越来越严重。 本发明的关键是在狭窄的硅化物栅极中，在较大的垂直表面积上传播高度有害的机械应力。 这是通过使用用于栅极的薄/厚双重多晶硅堆叠实现的，由此，下部薄多晶硅栅极层不被硅化，并且随后硅化上部厚多晶硅层。 在有源源极 - 漏极区域的硅化期间，使用绝缘层来防止下部薄多晶硅栅极的硅化。 同样的绝缘层也用于通过在用于间隔物形成的干蚀刻期间保护下部薄多晶硅栅极层的表面晶界不被聚合物填充而避免机械应力的另一个原因。 高堆叠栅极结构允许硅化物引起的应力更安全地远离有源器件。

公开(公告)号：US6153485A

公开(公告)日：2000-11-28

申请号：US188522

申请日：1998-11-09

申请人： Kin-Leong Pey ,  Soh-Yun Siah

发明人： Kin-Leong Pey ,  Soh-Yun Siah

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L29/66545

摘要： A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.

摘要翻译： 其中S / D硅化物接触形成在比栅极硅化物接触的单独硅化物步骤中的自对准硅化物工艺的方法。 优选地，在S / D区域上形成TiSi 2，并且通过蚀刻多个电极上的侧壁间隔物，在多个电极（线或栅极）上形成TiSi 2或CoSi 2。 本发明具有两个硅化物步骤。 在S / D区域上形成TiSi2，同时栅电极被氮化硅盖层保护。 接下来，形成在S / D区域上的ILD层。 层间电介质（ILD）层，盖层和栅电极侧壁上的间隔物被回蚀刻。 本发明具有用于间隔物组成的两个实施例。 在第二硅化物步骤中，在电极的顶部和侧壁上形成硅化钛（TiSix或TiSi2）或硅化钴（CoSix或CoSi2）。 本发明的一个关键特征是栅极接触硅化物形成在电极的顶部和侧壁上。

公开(公告)号：US6110811A

公开(公告)日：2000-08-29

申请号：US94466

申请日：1998-06-11

申请人： Kin-Leong Pey

发明人： Kin-Leong Pey

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/66515 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28562 ,  H01L29/665

摘要： A method for improving the quality and uniformity of a silicide film in the fabrication of a silicided polysilicon gate and source/drain regions in an integrated circuit device is described. A polysilicon gate electrode is provided on the surface of a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate adjacent to the gate electrode. A layer of titanium is deposited over the surfaces of the substrate. The substrate is annealed whereby the titanium layer is transformed into a first titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the first titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions. A second titanium silicide layer is selectively deposited on the first titanium silicide layer to complete formation of the silicided gate electrode and source and drain regions in the fabrication of an integrated circuit device. The first titanium silicide layer reduces or eliminates the effect of the polysilicon and silicon surface effects allowing for a higher quality and more uniform second titanium silicide layer.

摘要翻译： 描述了在集成电路器件中硅化多晶硅栅极和源极/漏极区域的制造中改善硅化物膜的质量和均匀性的方法。 在半导体衬底的表面上设置多晶硅栅电极。 源极和漏极区域形成在与栅电极相邻的半导体衬底内。 在衬底的表面上沉积一层钛。 将衬底退火，由此将钛层转变为第一钛硅化物层，除了钛层覆盖在间隔物之外。 剥离覆盖间隔物的钛层仅在栅电极的顶表面和覆盖源区和漏区的半导体衬底的顶表面上离开第一硅化钛层。 在第一硅化钛层上选择性地沉积第二钛硅化物层，以在集成电路器件的制造中完成硅化物栅极电极和源极和漏极区域的形成。 第一钛硅化物层降低或消除了多晶硅和硅表面效应的影响，从而允许更高质量和更均匀的第二硅化钛层。

公开(公告)号：US06316811B1

公开(公告)日：2001-11-13

申请号：US09596905

申请日：2000-06-19

申请人： Kin-Leong Pey

发明人： Kin-Leong Pey

IPC分类号： H01L2976

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for improving the quality and uniformity of a silicide film in the fabrication of a silicided polysilicon gate and source/drain regions in an integrated circuit device is described. A polysilicon gate electrode is provided on the surface of a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate adjacent to the gate electrode. A layer of titanium is deposited over the surfaces of the substrate. The substrate is annealed whereby the titanium layer is transformed into a first titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the first titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions. A second titanium silicide layer is selectively deposited on the first titanium silicide layer to complete formation of the silicided gate electrode and source and drain regions in the fabrication of an integrated circuit device. The first titanium silicide layer reduces or eliminates the effect of the polysilicon and silicon surface effects allowing for a higher quality and more uniform second titanium silicide layer.

摘要翻译： 描述了在集成电路器件中硅化多晶硅栅极和源极/漏极区域的制造中改善硅化物膜的质量和均匀性的方法。 在半导体衬底的表面上设置多晶硅栅电极。 源极和漏极区域形成在与栅电极相邻的半导体衬底内。 在衬底的表面上沉积一层钛。 将衬底退火，由此将钛层转变为第一钛硅化物层，除了钛层覆盖在间隔物之外。 剥离覆盖间隔物的钛层仅在栅电极的顶表面和覆盖源区和漏区的半导体衬底的顶表面上离开第一硅化钛层。 在第一硅化钛层上选择性地沉积第二钛硅化物层，以在集成电路器件的制造中完成硅化物栅极电极和源极和漏极区域的形成。 第一钛硅化物层降低或消除了多晶硅和硅表面效应的影响，从而允许更高质量和更均匀的第二硅化钛层。

公开(公告)号：US6025267A

公开(公告)日：2000-02-15

申请号：US115724

申请日：1998-07-15

申请人： Kin-Leong Pey ,  Soh-Yun Siah ,  Yong-Meng Lee

发明人： Kin-Leong Pey ,  Soh-Yun Siah ,  Yong-Meng Lee

IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/46

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A method for forming self-aligned, metal silicide, (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, on polysilicon gate structures, and on source/drain regions, located in a second region of a semiconductor substrate, has been developed. A composite insulator shape, comprising an overlying silicon nitride layer, and an underlying TEOS deposited, silicon oxide layer, is used to block polysilicon, as well as silicon regions, in the second region of the semiconductor substrate, from salicide formation. Unwanted silicon oxide spacers, created on the sides of polysilicon gate structures, during the patterning of the composite insulator shape, is selectively removed using dilute hydrofluoric acid solutions.

摘要翻译： 一种在多晶硅栅结构上形成位于半导体衬底的第一区域中的自对准金属硅化物，（硅化物）层，多晶硅栅极结构上的源极/漏极区域，同时避免形成硅化物的方法， 并且已经开发了位于半导体衬底的第二区域中的源极/漏极区域上。 使用包括上覆氮化硅层和下面的TEOS沉积的氧化硅层的复合绝缘体形状来阻挡半导体衬底的第二区域中的多晶硅以及硅区域，从硅化物形成。 使用稀氢氟酸溶液选择性地去除在复合绝缘体形状的图案化期间在多晶硅栅极结构的侧面上产生的不需要的氧化硅间隔物。